/dts-v1/;

/ {
    #address-cells = <2>;
    #size-cells = <2>;

    gic: gic {
        #interrupt-cells = <3>;
        interrupt-controller;
        phandle = <0xfde8>;
    };

//////  reserved-memory {
//////      #address-cells = <2>;
//////      #size-cells = <1>;
//////      ranges;
//////
//////      wf1basepp: wf1basepp_shm@0 {
//////          no-map;
//////          reg = <0x0 0x30080000 0xA00000>;/*10M*/
//////          xen,path = "/reserved-memory/wf1basepp_shm@0";
//////          xen,reg = <0x0 0x30080000 0xA00000 0x0 0x30080000>;
//////          xen,force-assign-without-iommu;
//////      };
//////  };

    passthrough {
        compatible = "simple-bus", "xlnx,zynqmp";
        ranges;
        #address-cells = <2>;
        #size-cells = <2>;

        zynqmp-firmware {
            compatible = "xlnx,zynqmp-firmware";
            #power-domain-cells = <0x1>;
            method = "smc";
            phandle = <0xc>;

            reset-controller {
                compatible = "xlnx,zynqmp-reset";
                #reset-cells = <0x1>;
                phandle = <0x1a>;
            };

            clock-controller {
                #clock-cells = <0x1>;
                compatible = "xlnx,zynqmp-clk";
                clocks = <0x6 0x7 0x8 0x9 0xa>;
                clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
                linux,phandle = <0x3>;
                phandle = <0x3>;
            };
        };

        pss_ref_clk {
            compatible = "fixed-clock";
            #clock-cells = <0x0>;
            clock-frequency = <33330000>; // 33333333
            phandle = <0x6>;
        };

        video_clk {
            compatible = "fixed-clock";
            #clock-cells = <0x0>;
            clock-frequency = <27000000>;
            phandle = <0x7>;
        };

        pss_alt_ref_clk {
            compatible = "fixed-clock";
            #clock-cells = <0x0>;
            clock-frequency = <0x0>;
            phandle = <0x8>;
        };

        aux_ref_clk {
            compatible = "fixed-clock";
            #clock-cells = <0x0>;
            clock-frequency = <27000000>;
            phandle = <0x9>;
        };

        gt_crx_ref_clk {
            compatible = "fixed-clock";
            #clock-cells = <0x0>;
            clock-frequency = <108000000>;
            phandle = <0xa>;
        };

        pcie@fd0e0000 {
            compatible = "xlnx,nwl-pcie-2.11";
            status = "okay";
            #address-cells = < 0x03 >;
            #size-cells = < 0x02 >;
            #interrupt-cells = < 0x01 >;
            msi-controller;
            device_type = "pci";
            phandle = <0x17>;

            interrupt-parent = < &gic >;
            interrupts = <0x00 0x76 0x04>,
                                        <0x00 0x75 0x04>,
                                        <0x00 0x74 0x04>,
                                        <0x00 0x73 0x04>,
                                        <0x00 0x72 0x04>;
            interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
            msi-parent = <0x17>;

            reg = <0x00 0xfd0e0000 0x00 0x1000>,
                  <0x00 0xfd480000 0x00 0x1000>,
                  <0x80 0x00000000 0x00 0x1000000>;
            reg-names = "breg", "pcireg", "cfg";

            ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000   /* non-prefetchable memory */
                      0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>; /* prefetchable memory */
            bus-range = < 0x00 0xff >;

            interrupt-map-mask = < 0x00 0x00 0x00 0x07 >;
            interrupt-map = <0x00 0x00 0x00 0x01 0x18 0x01>,
                            <0x00 0x00 0x00 0x02 0x18 0x02>,
                            <0x00 0x00 0x00 0x03 0x18 0x03>,
                            <0x00 0x00 0x00 0x04 0x18 0x04>;

            power-domains = <0xc 0x3b>;
            clocks = <0x3 0x17>;

            xen,path = "/amba/pcie@fd0e0000";
            xen,reg = <0x80 0x00000000 0x0 0x1000000 0x80 0x00000000>,
                      <0x0 0xe0000000 0x0 0x1000000 0x0 0xe0000000>,
                      <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd0e0000>,
                      <0x0 0xfd480000 0x0 0x1000 0x0 0xfd480000>;

            /* tie dom0less passthrough device to dom0 device tree. */
            /* phys-addr[2 cells] size [1 cell] guest-phys-addr[2 cells] */
            /* NOTICE: missing mappint from 0x6_00000000 to 0x7_FFFFFFFF */
            legacy-interrupt-controller {
                interrupt-controller;
                #address-cells = < 0x0 >;
                #interrupt-cells = < 0x1 >;
                phandle = <0x18>;
            };
        };
    };
};