Introduction
This page gives an overview of clk_wiz driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/release-2020.1/XilinxProcessorIPLib/drivers/clk_wiz
Driver source code is organized into different folders. Below diagram shows the clk_wiz driver source organization
ospipsv
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files
Features Supported
- Accepts up to two input clocks and up to
seven output clocks per clock network. - Provides an AXI4-Lite interface for
dynamically reconfiguring the clocking
primitives for Multiply, Divide, Phase Shift/
Offset, or Duty Cycle.
Features not supported
- None
Test cases
- xclk_wiz_intr_example - This example tests the clock monitoring example.
- xclk_wiz_versal_example.- Example to set the output frequency to a specific rate for versal platform.
Change Log
2020.1
2020.2
- f205462 - clk_wiz: Add a function clk for getting the clock in Hz
- e3e7843 - clk_wiz: Modify Makefile to support parallel make execution
- a466514 - clk_wiz: Clock wizard driver updates (add enable disable and set rate capability)
Related Links