versal uart Driver
Introduction
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates. The server-based system applications (SBSA) functionality is defined by the Arm® architecture.
HW IP Features
32 deep ×8-bit wide transmit FIFO • 32 deep ×12-bit wide receive FIFO
Standard asynchronous communication bits (start, stop and parity)
Independent interrupt masking:
○ Transmit and receive FIFOs
○ Receive timeout, modem status, and error condition
False start bit detection •
Line break generation and detection
Modem control functions CTS, DCD, DSR, RTS, DTR, and RI
Features supported in driver
Uart send recieve
Standard asynchronous communication bits (start, stop and parity)
Line break generation and detection
Modem control functions CTS, DCD, DSR, RTS, DTR, and RI
Missing Features, Known Issues and Limitations
None
Kernel Configuration
To enable the uartlite driver in the linux kernel you either have to integrate it or build it as kernel module (.ko). You can enable it with:
make menuconfig ---> Device Drivers ---> Character devices ---> Serial drivers ---> ARM AMBA PL010 serial port support |
Or you can do this in the .config file with either of the following lines:
# integrate into the kernel SERIAL_AMBA_PL010=y # build as loadable module SERIAL_AMBA_PL010=m |
Devicetree
Here's how the devicetree entry could look like.
https://www.kernel.org/doc/Documentation/devicetree/bindings/serial/pl011.yaml
serial@80120000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80120000 0x1000>;
interrupts = <0 11 4>;
dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
dma-names = "rx", "tx";
clocks = <&foo_clk>, <&bar_clk>;
clock-names = "uartclk", "apb_pclk";
};
|
Mainline Status
This driver is currently in sync with mainline kernel except for the following:
tty: pl011: Add support for xilinx uart
tty: pl011: Add support for parity configuration
tty: pl011: Add support for configurable wordlength
Change Log
2020.2
None