he LogiCORE™ IP Clocking Wizard generates HDL source code to configure a clock circuit to user requirements. The wizard can either automatically select an appropriate clocking primitive and configure buffering, feedback, and timing parameters for a clocking network, or help the user configure the attributes for a manually selected primitive.
Table of Contents
HW IP Features
Accepts up to two input clocks and up to seven output clocks per clock network
Automatically chooses the correct clocking primitive for a selected device and configures the clocking primitive based on user-selected clocking features
Calculates VCO frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements
Implements an overall configuration that supports phase shift and duty cycle requirements
Provides the ability to override an auto-selected clock primitive as well as any calculated attribute
Known Issues and limitations
None
Kernel Configuration
. The following steps may be used to enable the driver in the kernel configuration
CONFIG_COMMON_CLK_XLNX_CLKWZRD=y |
Devicetree
clock-generator@40040000 {
#clock-cells = <1>;
reg = <0x40040000 0x1000>;
compatible = "xlnx,clocking-wizard";
speed-grade = <1>;
clock-names = "clk_in1", "s_axi_aclk";
clocks = <&clkc 15>, <&clkc 15>;
clock-output-names = "clk_out1", "clk_out2",
"clk_out3", "clk_out4", "clk_out5",
"clk_out6", "clk_out7";
};
|
Test procedure
Mainline Status
This driver is currently in sync with mainline kernel except for the following:
Moving the driver to clock from staging.
Change Log
2020.1
Summary:
clk: clock-wizard: Remove a unnessary type cast
clk: clock-wizard: Update the fixed factor divisors
clk: clock-wizard: Remove the hardcoding of the clock outputs
clk: clock-wizard: Add support for fractional support
clk: clock-wizard: Add support for dynamic reconfiguration
clk: clock-wizard: Fix kernel-doc warning
clk: clock-wizard: Move the clockwizard to clk
Commits:
2020.2
None
Related Links