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The LogiCORE IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture (AMBA) specification’s Advanced eXtensible Interface (AXI) and provides the controller interface for asynchronous serial data transfer. This soft LogiCORE IP core is designed to interface with the AXI4-Lite protocol.



Device tree

serial@40600000 {
	clock-frequency = <100000000>;
	clocks = <&clk_bus_0>;
	compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
	current-speed = <115200>;
	device_type = "serial";
	port-number = <0>;
	reg = <0x40600000 0x10000>;

Test procedure

  • None


  • AXI interface is based on the AXI4-Lite specification

  • One transmit and one receive channel (full duplex)

  • 16-character transmit and receive FIFOs

  • Configurable number of data bits (5-8) in a character

  • Configurable parity bit (odd or even or none)

  • Configurable baud rate

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