Introduction
This page gives an overview of axi-quad spi driver which is available as part of the Xilinx Vivado and Vitis distribution.
Source path for the driver:https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/spi
Driver source code is organized into different folders. Below diagram shows the qspipsu driver source organization
spi
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- Doc - Provides the API and data structure details
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Examples - Reference application to show how to use the driver APIs and calling sequence
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Source - Driver source files
Features Supported
The controller driver will be exclusive to GQSPI including API’s to be used for configuring the host controller and transmitting the data.
Commands Supported:
The following list of basic commands are supported by the Standalone driver:
Read Identification
Read Page
Program Page
Erase (Chip/Die/Bulk Erase)
Read Status
EAR Register Access
Controller Features Supported:
The following features are supported in the QSPI Standalone driver.
DMA access (aligned address only)
IO access
Configurable clock
Configurable bus width
Interrupts – will be chosen and enabled internally
Example Applications:
Generic register read/write operations
3 byte and 4 byte addressing
Flash configurations illustrated in examples – Single
Known issues and Limitations
The standalone driver supports Axi-spi and AXI Quad spi
Test cases
Sample output of test cases that are taken from examples folder specified above
XSPI Stm Flash Example Test |
XSPI Numonyx Flash Quad Example Test Successfully ran XSPI Numonyx Flash Quad Example Test |
XSPI Windbond Flash Quad Example Test Successfully ran XSPI Flash Quad Example Test |
XSPI Atmel Flash Example Test |
Change Log
2019.2
Summary
Removed master inhibit dependency while writing to DTR.
Fixed compilation error in axi-spi interrupt example.
Commits
2020.1
Summary
Updating license content to SPDX based licensing.
Commits
2020.2
Summary
None
Commits
None