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In this wiki page, we cover the customization of the bitstream for use on custom boards as well as usage on the Xilinx evaluation boards, ZCU111, ZCU208 and ZCU216. The installation and general usage of the RF analyzer GUI is covered in UG1309.
Installation
Please refer to UG1309, ”Installing the RF Analyzer” section.
First time starting RF analyzer, Vivado path setup
RF analyzer requires the hardware sever as a minimum. The hardware server is installed by default with the Vivado lab edition, or Vivado System Edition.
The first time RF analyzer GUI is launched, the Vivado install path should be set:
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This path is written into the RF_Analyzer.ini file present in the install directory, at the same level as the executable RF_Analyzer.exe.
Board detection and device configuration
Once the Vivado path is setup and the GUI starts, the “hardware target” tab opens. Hitting “connect” (#1 in the image below) will detect the JTAG cables, devices present in the JTAG chain, their status (configured/unconfigured), and if an RF analyzer compatible design is present. The results of this detection is displayed in the “Hardware” sub-window (#2 in the image below).
We can then select the part we want to configure in the “Hardware” sub-window (#2), select the bitstream (#3) and hit download bitstream (#4).
For this quickstart, we can use the pre-built bitstreams provided within the installation directory of RF analyzer. They are located in <RF_Analyzer Install directory>\Protocol\RFAnalyzer\bitstreams. To generate your own bitstream, please see the section below “Custom Bitstream Generation”.
Once the part is configured, we can select the Microblaze associated with the part and hit “Select Target” (#5). RF analyzer will read the RFDC IP configuration.
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Generation and Acquisition
When device configuration reading is complete, you will see a screen similar to the following:
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Note that the external reference clocks should be present and their frequencies match the frequencies expected by the IP configuration. If not, the tiles might not be fully up and running.
To configure external clocks on the Xilinx evaluation board, please refer to “External Clock configuration on Xilinx evaluation boards” section of this wiki.
For Xilinx evaluation board setup, please refer to the relevant board section of this wiki.
The right-hand side of the window is used to display information about selected blocks, for example a single-click on “ADC Tile 0” will show:
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DAC Signal Generation
Double-click on DAC Tile 0.
Double-click on DAC channel 0, (avoiding the selectable sub-blocks).
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Click on "Generate" to start signal generation by the DAC.
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ADC Signal Acquisition
Double-click on ADC tile 0.
Double-click on ADC 0, (avoiding the selectable sub-blocks).
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Click “Acquire” to see the signal that has been looped back from DAC Tile 0: DAC 0.
Select suitable windowing to reduce the distortion of the spectrum due to incoherence.
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Custom Bitstream Generation
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