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Tutorial: Modules 1-5 of Introduction to NoC DDRMC Design Flow
Blog: Basic read/write to AXI BRAM from PS-APU through NoC in Versal
CEDStore: AXI DMA on VCK190
Tutorial: Versal Embedded Design, section on Versal ACAP CIPS and NoC (DDR) IP Core Configuration
CEDStore: VCK190/VMK190 Configurable Example Design in Vivado
CEDStore: Simulating with the CIPS Verification IP
Example: Versal Network on Chip/Multiple DDR Memory Controllers Tutorial
System Integration and Validation
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