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The purpose of this page is to describe the Linux DRM driver for the Xilinx DisplayPort 1.4 Tx Subsystem Soft IP for the Zynq UltraScale+ MPSoC.

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The purpose of this page is to describe the Linux DRM driver for Xilinx DisplayPort 1.4 TX Subsystem Soft IP for Zynq Ultrascale+ MPSoC.

The DisplayPort 1.4 Tx Subsystem implements functionality of a video source as defined by the Video Electronics Standards Association (VESA)'s DisplayPort standard v1.4 and supports driving resolutions of up to Full Ultra HD (FUHD) at 30 fps. The subsystem is a hierarchical IP that bundles a collection of DP TX-related IP sub-cores and outputs them as a single IP. The subsystem takes incoming video stream and transfers them to an DP stream. The stream is then forwarded to the video PHY layer. Below is the block diagram of DisplayPort 1.4 Tx Subsystem.


DisplayPort Tx Subsystem Block Diagram

Figure 1. Block diagram of DisplayPort 1.4 Tx Subsystem


The DP 1.4 Tx Subsystem is a MAC subsystem which works with a Video PHY Controller (PHY) to create a video connectivity system. The DP 1.4 Tx Subsystem is tightly coupled with the Xilinx Video PHY Controller, which itself is independent and offer flexible architecture with multiple-protocol support. Both MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 2. Block diagram of MAC Interface with PHY

Driver Overview

DP Tx is the last node in the display pipeline. The Linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver (bridge driver name : xlnx) and implements the encoder/connector interface. The subsystem includes the video timing generator and Tx sub-core. Driver implements the DRM callbacks to read the display EDID and present it to the framework anytime a display is connected. It works in tandem with the DRM bridge driver to validates each mode listed in the EDID and reject unsupported modes.

The display pipeline contains the AXI remapper IP before the  DP 1.4 Tx subsystem . The AXI remapper IP converts the input number of ppc to output number of ppc .Note that  remapper IP in display pipeline converts from any ppc ( ex :1,2,3,4) to  4 ppc only .

On mode change request from user application driver works in conjunction with DRM framework to validate the requested mode to ensure the stream can be generated by Tx core and is supported by the attached display. If requested mode is supported, the driver On mode change request from user application driver works in conjunction with DRM framework to validate the requested mode to ensure the stream can be generated by Tx core and is supported by the attached display. If requested mode is supported, the driver will configure Tx sub-core for new mode ,the internal video timing controller (VTC) to generate requisite video timing for it and .It also configures the remapper IP with required input ppc for the new mode. It also configures the PHY PHY layer for the new mode and manages all required interaction between MAC & PHY layer.

This Xilinx LogiCORE IP Video remapper core is used for converting the variable inbound PPC ( 1, or 2 or 4 ) from DP core to outbound PPC 4 . As Framebuffer write IP always expects 4 PPC as input.
After mode setup is complete PHY state machine is reset and put into a wait state awaiting the reference clock for the new mode from an external clock source. DRM framework requests the registered clock producer  to generate the clock for desired mode. 

IP/Driver Features


IP Feature2020.12020.2
IP Version Supported2.13.0
Supports AXI4-Stream, native video input interfacesAxi-Stream Video OnlyAxi-Stream Video Only
Support for 2 pixel per sampleYesYes

Support color space for RGB, YUV 4:4:4, YUV 4:2:2,Y-only 

YesYes
Audio support for 2 to 8 channelstYesYes
8, 10, 12, and 16-bit Deep-color support8 and 10-bit only 8 and 10-bit only 
Support for 16-bit GT width.YesYes
Support HDCP 2.xNoNo
HDCP in MST mode NoNo
In-band stereoNoNo
Video AXI4-Stream interface is not scalable with dynamic pixel mode selectionNoNo
Dual-pixel splitter in native video modeNoNo
Supported resolution up to 8k30YesYes
Supported interlaced mode NoNo

Missing Features / Known Issues / Limitations in Driver

  • This driver does't support following features 
    • HDCP 
    • Audio

Kernel Configuration Options for Driver

2019.2 and onwards: Supports ONLY the new Xilinx DRM framework driver and PL crtc and can be enabled via following configurations options CONFIG_DRM_XLNX and CONFIG_DRM_XLNX_PL_DISP

The above defined options will only enable the new DRM framework. Since DP Tx driver is now added as an out-of-tree kernel module, there is no kernel configuration required.

Building Driver Modules 

Code Block
themeMidnight
export TOP_DIR = $(shell pwd)                                                                                                                             
BOARD_NAME := zcu102                                                          
export ARCH = arm64                                                                                                                                           
GCC_PREFIX = <cross-compiler path>
                                                                                  
export DP_SOURCE := $(TOP_DIR)/dp-modules                                     
export KERNEL_SOURCE := $(TOP_DIR)/linux-xlnx                                 
export OUTPUT_DIR := $(TOP_DIR)/output                                        
export KERNEL_OUTPUT := $(OUTPUT_DIR)/linux-xlnx-$(ARCH)                      
                                                                                  
kernel:                                                                       
        ARCH=$(ARCH) CROSS_COMPILE=$(GCC_PREFIX) make -C $(KERNEL_SOURCE) xilinx_zynqmp_defconfig O=$(KERNEL_OUTPUT)
        ARCH=$(ARCH) CROSS_COMPILE=$(GCC_PREFIX) make -j 40 -C $(KERNEL_SOURCE) O=$(KERNEL_OUTPUT) Image
        ARCH=$(ARCH) CROSS_COMPILE=$(GCC_PREFIX) make -j 40 -C $(KERNEL_SOURCE) O=$(KERNEL_OUTPUT) modules
modules:                                                                      
        ARCH=$(ARCH) CROSS_COMPILE=$(GCC_PREFIX) make -j 40 -C $(KERNEL_SOURCE) M=$(DP_SOURCE) O=$(KERNEL_OUTPUT) modules
        find $(DP_SOURCE) -type f -name '*.o' -delete                         
        find $(DP_SOURCE) -type f -name '*.cmd' -delete                       
        find $(DP_SOURCE) -type f -name 'Modules' -delete                     
        find $(DP_SOURCE) -type f -name 'Module.*' -delete                    
        find $(DP_SOURCE) -type f -name '*.order' -delete                     
        find $(DP_SOURCE) -type f -name '*.mod.c' -delete                     
        find $(DP_SOURCE) -type f -name '*.mod' -delete

  • run the below command to build the kernel

    • $ make kernel
  • run the below command to build the dp-modules 
    • $make modules
  • Insert the above built modules after the kernel boots up, insert them in  a sequence as shown below 

    • insmod phy-xilinx-vphy.ko

    • insmod xilinx_dp.ko

  • Now the DP Tx driver is ready to use.

Device Tree Binding

The dts node should be defined with correct hardware configuration. An example device tree node is documented in

2020.1: Documentation/devicetree/bindings/xlnx,v-dp-tx-ss.txt

2020.2: Documentation/devicetree/bindings/xlnx,dp-tx.yaml

Example Design Architecture 

Image RemovedImage Added

Figure 3. DisplayPort Tx example design architecture 

Test Procedure

DP-Tx can be manually configured to generate the required mode. An open source utility like modetest can be used to configure the display pipeline.

  • DDR ==> remapper ==>FB_Rd (DMA)==>DP _Tx


2020.1 and on wards Sample command to set a mode is shown below

Code Block
themeMidnight
%> modetest -M xlnx -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format>

example command 

Code Block
themeMidnight
%> modetest -M xlnx -s 3135:1920x1080-60@BG24

Above command will generate a color bar pattern at requested resolution in DDR, configures the DMA to read the frame from DDR and configures the DP Tx for said resolution. As a final result Color Bar at defined resolution should be visible on screen.

Driver also supports changing output color formats dynamically. Available output color formats supported by DMA engine can be determined using modetest utility as shown below

Code Block
languagexml
themeMidnight
root@xilinx-zcu102-2020_1:~# modetest -M xlnx
Encoders:
id_2:/media# modetest -M xlnx
Encoders:
id      crtc    type    possible crtcs  possible clones
34      0       TMDS    0x00000001      0x00000000

Connectors:
id      encoder status          name            size (mm)       modes   encoders
35      0       connected       DP-1            700x390         39      crtc34
  modes:
type    possible crtcs  possible clonesname 30refresh (Hz) hdisp hss hse htot 0vdisp vss vse vtot)
  7680x4320 TMDS29.93 7680 7710 7720 0x000000017880 4320 4323 4328 4368 1030240 0x00000000flags: phsync, nvsync; Connectorstype: idpreferred, driver
  7680x4320  encoder status          name            size (mm)       modes   encoders
31      0       connected       DP-1            700x390         39      30
  modes:
        name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
  7680x4320 30 7680 7710 7720 7880 4320 4323 4328 4368 1030240 flags: phsync, nvsync; type: preferred, driver
  7680x4320 24 7680 7728 7760 7880 4320 4323 4328 4369 82625024.00 7680 7728 7760 7880 4320 4323 4328 4369 826250 flags: phsync, nvsync; type: preferred, driver
  3840x2160 60.00 3840 3888 3920 4000 2160 2163 2168 2222 533250 flags: phsync, nvsync; type: preferred, driver
  3840x4320 60.00 3840 3888 3920 4040 4320 4323 4333 4368 1058790 flags: phsync, nvsync; type: driver
  3840x4320 48.00 3840 3888 3920 4040 4320 4323 4333 4418 856720 flags: phsync, nvsync; type: driver
  3840x2160 29.98 3840 3888 3920 4000 2160 2163 2168 2191 262750 flags: phsync, nvsync; type: driver
  2560x1440 59.95 2560 2608 2640 2720 1440 1443 1448 1481 241500 flags: phsync, nvsync; type: driver
  1920x1200 59.88 1920 2056 2256 2592 1200 1203 1209 1245 193250 flags: nhsync, pvsync; type: driver
  2048x1080 59.99 2048 2096 2128 2208 1080 1083 1093 1111 147160 flags: phsync, nvsync; type: preferred, driver
  3840x21602048x1080 6023.90 38402048 38882096 39202128 40002208 21601080 21631083 21681093 22221099 53325058000 flags: phsync, nvsync; type: preferred, driver
  3840x43201920x1080 60.00 38401920 38882008 39202052 40402200 43201080 43231084 43331089 43681125 1058790148500 flags: phsyncnhsync, nvsync; type: driver
  3840x43201920x1080 4860.00 38401920 38882008 39202052 40402200 43201080 43231084 43331089 44181125 856720148500 flags: phsync, nvsyncpvsync; type: driver
  3840x21601920x1080 3059.94 38401920 38882008 39202052 40002200 21601080 21631084 21681089 21911125 262750148352 flags: phsync, nvsyncpvsync; type: driver
  2560x1440 60 2560 26081920x1080 50.00 1920 2448 2492 2640 27201080 14401084 14431089 14481125 1481148500 241500 flags: phsync, nvsyncpvsync; type: driver
  1920x12001920x1080 6024.00 1920 20562558 22562602 25922750 12001080 12031084 12091089 12451125 19325074250 flags: nhsyncphsync, pvsync; type: driver
  2048x10801920x1080 6023.98 20481920 20962558 21282602 22082750 1080 10831084 10931089 11111125 14716074176 flags: phsync, nvsyncpvsync; type: driver
  2048x10801600x1200 2460.00 20481600 20961664 21281856 22082160 10801200 10831201 10931204 10991250 58000162000 flags: phsync, nvsyncpvsync; type: driver
  1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 1485001680x1050 59.95 1680 1784 1960 2240 1050 1053 1059 1089 146250 flags: nhsync, nvsyncpvsync; type: driver
  1920x10801280x1024 6075.02 19201280 20081296 20521440 22001688 10801024 10841025 10891028 11251066 148500135000 flags: phsync, pvsync; type: driver
  1920x10801280x1024 60.02 19201280 20081328 20521440 22001688 10801024 10841025 10891028 11251066 148352108000 flags: phsync, pvsync; type: driver
  1920x10801280x800 5059.81 19201280 24481352 24921480 26401680 1080800 1084803 1089809 1125831 14850083500 flags: phsyncnhsync, pvsync; type: driver
  1920x10801280x720 2460.00 19201280 25581390 26021430 27501650 1080720 1084725 1089730 1125750 74250 flags: phsync, pvsync; type: driver
  1920x10801280x720 2459.94 19201280 25581390 26021430 27501650 1080720 1084725 1089730 1125750 74176 flags: phsync, pvsync; type: driver
  1600x12001280x720 6050.00 16001280 16641720 18561760 21601980 1200720 1201725 1204730 1250750 16200074250 flags: phsync, pvsync; type: driver
  1680x10501024x768 6075.03 16801024 17841040 19601136 22401312 1050768 1053769 1059772 1089800 14625078750 flags: nhsyncphsync, pvsync; type: driver
  1280x10241024x768 7560.00 12801024 12961048 14401184 16881344 1024768 1025771 1028777 1066806 13500065000 flags: phsyncnhsync, pvsyncnvsync; type: driver
  1280x1024800x600 6075.00 1280800 1328816 1440896 16881056 1024600 1025601 1028604 1066625 10800049500 flags: phsync, pvsync; type: driver
  1280x800800x600 60.32 1280800 1352840 1480968 16801056 800600 803601 809605 831628 8350040000 flags: nhsyncphsync, pvsync; type: driver
  1280x720720x576 6050.00 1280720 1390732 1430796 1650864 720576 725581 730586 750625 7425027000 flags: phsyncnhsync, pvsyncnvsync; type: driver
  1280x720720x576 6050.00 1280720 1390732 1430796 1650864 720576 725581 730586 750625 7417627000 flags: phsyncnhsync, pvsyncnvsync; type: driver
  1280x720720x480 5060.00 1280720 1720736 1760798 1980858 720480 725489 730495 750525 7425027027 flags: phsyncnhsync, pvsyncnvsync; type: driver
  1024x768720x480 7560.00 1024720 1040736 1136798 1312858 768480 769489 772495 800525 7875027027 flags: phsyncnhsync, pvsyncnvsync; type: driver
  1024x768720x480 6059.94 1024720 1048736 1184798 1344858 768480 771489 777495 806525 6500027000 flags: nhsync, nvsync; type: driver
  800x600720x480 7559.94 800720 816736 896798 1056858 600480 601489 604495 625525 4950027000 flags: phsyncnhsync, pvsyncnvsync; type: driver
  800x600640x480 6075.00 800640 840656 968720 1056840 600480 601481 605484 628500 4000031500 flags: phsyncnhsync, pvsyncnvsync; type: driver
  720x576640x480 5060.00 720640 732656 796752 864800 576480 581490 586492 625525 2700025200 flags: nhsync, nvsync; type: driver
  720x576640x480 5059.94 720640 732656 796752 864800 576480 581490 586492 625525 2700025175 flags: nhsync, nvsync; type: driver
  720x480640x480 6059.94 720640 736656 798752 858800 480 489490 495492 525 2702725175 flags: nhsync, nvsync; type: driver
  720x480720x400 6070.08 720 736738 798846 858900 480400 489412 495414 525449 2702728320 flags: nhsync, nvsyncpvsync; type: driver
  720x480props:
60 720 736 798 858 480 489 495 5251 27000 flagsEDID:
nhsync, nvsync; type: driver   720x480 60 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driverimmutable blob
     640x480 75 640 656 720 840 480 481 484 500 31500 flagsblobs: nhsync, nvsync; type: driver

           640x480 60 640 656 752 800value:
480 490 492 525 25200 flags: nhsync, nvsync; type: driver   640x480 60 640 656 752 800 480 490 492 525 25175 flags: nhsync,00ffffffffffff0010ac47414c353730
nvsync; type: driver   640x480 60 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type: driver   720x400 70201b0104b54627783a7645ae5133ba26
720 738 846 900 400 412 414 449 28320 flags: nhsync, pvsync; type: driver   props:        0d5054a54b008100b300d100a9408180
1 EDID:                 flags: immutable blob    d1c0010101014dd000a0f0703e803020
            blobs:            3500ba892100001a000000ff0046464e
      value:                  584d3738373037354c0a000000fc0044
      00ffffffffffff0010ac47414c353730                  454c4c205550333231384b0a000000fd
      201b0104b54627783a7645ae5133ba26                  00184b1eb46c010a2020202020200270
      0d5054a54b008100b300d100a9408180                  02031df150101f200514041312110302
      d1c0010101014dd000a0f0703e803020                  161507060123091f0783010000a36600
      3500ba892100001a000000ff0046464e                  a0f0701f8030203500ba892100001a56
      584d3738373037354c0a000000fc0044                  5e00a0a0a0295030203500ba89210000
      454c4c205550333231384b0a000000fd                  1a7c3900a080381f4030203a00ba8921
      00184b1eb46c010a2020202020200270                  00001aa81600a08038134030203a00ba
      02031df150101f200514041312110302                  892100001a0000000000000000000000
      161507060123091f0783010000a36600                  00000000000000000000000000000047
      a0f0701f8030203500ba892100001a56                  701279000012001682100000ff0edf10
      5e00a0a0a0295030203500ba89210000                  000000000044454c47414c3537300301
      1a7c3900a080381f4030203a00ba8921                  5070920184ff1dc7001d800900df102f
      00001aa81600a08038134030203a00ba                  0002000400c1420184ff1dc7002f801f
      892100001a0000000000000000000000                  00df10300002000400a84e0104ff0ec7
      00000000000000000000000000000047                  002f801f00df10610002000900979d01
      701279000012001682100000ff0edf10                  04ff0ec7002f801f00df102f00020009
      000000000044454c47414c3537300301                  00000000000000000000000000009890
      5070920184ff1dc7001d800900df102f  2 DPMS:
                flags: enum
   0002000400c1420184ff1dc7002f801f             enums: On=0 Standby=1 Suspend=2 Off=3
       00df10300002000400a84e0104ff0ec7         value: 3
        5 link-status:
    002f801f00df10610002000900979d01            flags: enum
           04ff0ec7002f801f00df102f00020009     enums: Good=0 Bad=1
                value: 000000000000000000000000000098900
        26 DPMSnon-desktop:
                flags: immutable enumrange
                enumsvalues: On=0 Standby=1 Suspend=2 Off=3
                value: 30
        54 link-statusTILE:
                flags: immutable enumblob
                enumsblobs:
Good=0 Bad=1
                value:
0         6 non-desktop:              313a313a323a313a303a303a33383430
  flags: immutable range                 values: 0 1 3a3433323000
               value: 0
        1921 CRTC_ID:
                flags: object
                value: 0
        3236 sync:
                flags: range
                values: 0 1
                value: 0
        3337 bpc:
                flags: enum
                enums: 6BPC=6 8BPC=8 10BPC=10 12BPC=12
                value: 8


CRTCs:
id      fb      pos     size
2933      0       (0,0)   (0x0)
   0nan 0 0 0 0 0 0 0 0 0 flags: ; type:
  props:
        2023 ACTIVE:
                flags: range
                values: 0 1
                value: 0
        24 MODE_ID:
                flags:  21 MODE_IDblob
                blobs:

                value:
        20 OUT_FENCE_PTR:
                flags: blobrange
                blobsvalues: 0 18446744073709551615
                value: 0
        1825 OUTVRR_FENCE_PTRENABLED:
                flags: range
                values: 0 184467440737095516151
                value: 0


Planes:
id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
2832      0       0       0,0             0,0     0               0x00000001
  formats: XB30 VU24 XV30 YUYV XV20 BG24
GREY Y10   props:
        79 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        1618 FB_ID:
                flags: object
                value: 0
        1719 IN_FENCE_FD:
                flags: signed range
                values: -1 2147483647
                value: -1
        1921 CRTC_ID:
                flags: object
                value: 0
        1214 CRTC_X:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        1315 CRTC_Y:
                flags: signed range
                values: -2147483648 2147483647
                value: 0
        1416 CRTC_W:
                flags: range
                values: 0 2147483647
                value: 1920
        1517 CRTC_H:
                flags: range
                values: 0 2147483647
                value: 1080
        810 SRC_X:
                flags: range
                values: 0 4294967295
                value: 0
        911 SRC_Y:
                flags: range
                values: 0 4294967295
                value: 0
        1012 SRC_W:
                flags: range
                values: 0 4294967295
                value: 125829120
        1113 SRC_H:
                flags: range
                values: 0 4294967295
                value: 70778880


Frame buffers:
id      size    pitch

root@xilinx-zcu102-2020_2:/media#

Refer Line "formats"that indicates the FrameBuffer DMA IP configuration supports XB30 VU24 XV30 YUYV XV20 BG24 GREY Y10 color formats. This setting is configured by the DMA driver device tree node property xlnx,vid-formats 

Debug Capability

 DP Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer

Boards Supported

Driver has been tested on following boards

  • zcu102 Rev-D
  • zcu102 Rev 1.0

Change Log

  • 2020.2

    • Summary:
      • Removed the support for external AXI Remapper 

Related Links