Table of Contents

Introduction

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• xclk_wiz_intr_example - This example tests the clock monitoring example.
• xclk_wiz_versal_example.- Example to set the output frequency to a specific rate for versal platform.

Change Log

2020.1

• 75b71e - clk_wiz: Add clocking wizard versal support
• b78dcfb - clk_wiz: Fix the makefile for windows

2020.2

• f205462 - clk_wiz: Add a function clk for getting the clock in Hz
• e3e7843 - clk_wiz: Modify Makefile to support parallel make execution
• a466514  - clk_wiz: Clock wizard driver updates (add enable disable and set rate capability)

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries