This page gives an overview of clk_wiz BareMetal driver.
Table of Contents
| Table of Contents | ||
|---|---|---|
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Introduction
This page gives an overview of clk_wiz driver which is available as part of the Xilinx Vivado and SDK distribution.
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| Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and .mdd fileyaml files |
examples | Example applications that show how to use the driver features |
| src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.
Driver Implementation
For a full list of features supported by this IP, please refer TRM
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This examples does basic rate setting of clocking wizard.
Expected Output
| Code Block |
|---|
------------------------------------------ CLK_WIZARD example ------------------------------------------ Successfully ran CLK_WIZARD example |
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NA
Performance
NA
Change Log
2023.2
embeddedsw/doc/ChangeLog at xilinx_v2023.2 · Xilinx/embeddedsw · GitHub
2023.1
None
2022.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.2/doc/ChangeLog#L90
2022.1
None
2021.1
None
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L1170
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