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Comment: added note about 2017.4


Note

If you need access to the 2017.4 BSP or the 2017.4 version of this wiki page, please contact your Xilinx FAE for assistance. 


Table of Contents

Table of Contents

Introduction

Zynq UltraScale+ MPSOC supports various type of reset from the simplest system reset to the much more complicated subsystem restart. In any system or subsystem which has a processor component and a programmable logic component, reset must entail both reset to the hardware as well as software. Reset to the hardware includes resetting of the processor, all peripherals associated with the system/subsystem, cleaning up of the memory as needed, and making sure that the interconnect is in a clean state, capable of routing traffic. Reset to the software results in the processor starting from the reset vector. However, designer must make sure that valid and clean code for system/subsystem is located at the reset vector in order to bring the system back to a clean running state.

Resets for Zynq UltraScale+ are broadly divided into two categories, full system resets and subsystem restarts.  Full system resets include Power On Reset (POR), system-reset and PS-only-reset. Subsystem restarts include APU subsystems and RPU subsystem restarts.  A subsystem in Zynq UltraScale+ is composed of all of the components of a particular operating system.  This page describes an example of how to design a project with multiple subsystems in it, and how to cleanly reset each one.


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