USB

Examples demonstrating Host & Device mode of the Versal PS USB controller.

VCK190

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2069987899/Versal+Linux+USB+Device+Driver+Examples

2021.1

Low Speed Peripherals

This repository contains VCK190 design files for PS and PL based LowSpeed IPs.

There are few available designs:

• axi_can - AXI CAN IP design subsytem with CIPS

• axi_can_fd - AXI CAN FD design subsystem with CIPS

• axi_i2c - AXI IIC IP design subsytem with CIPS

• ps_i2c - PS IIC design only

• ps_can_fd - PS CAN FD design only

• axi_uartlite - AXI UARTLite IP design subsytem with CIPS

• ps_sbsa_uart - PS UART IP design only

VCK190

https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/examples/versal/lowspeed_IPs

20202021.21

PS-GEM

This blog demonstrates how to bring up the PS-GEM in Versal.

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Bringing-Up-a-1G-Ethernet-Interface-on-a-Versal-device/ba-p/1092703

2020.2

PS and PL based Ethernet

This GitHub repo contains design files demonstrating a PS 10/100/1000BASE-T design utilizing the GEM over MIO to the TI PHY onboard on the VCK190

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet

20202021.21

PL 1G Ethernet

This project is about building Versal based AXI 1G/2.5G Ethernet Subsystem example design and testing it by targeting on VCK190 ACAP device using SGMII SFP

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet/tree/master/pl_eth_1G

2020.2

MRMAC

This blog covers the key differences between designing with UltraScale+ CMAC and Versal MRMAC.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Differences-between-Designing-with-UltraScale-CMAC-and-Versal/ba-p/1209580

2020.2