Boot Time From Dual Parallel QSPI

The goal is to be able to build a VCK190 design (QSPI dual Parallel) to reproduce the boot times outlined in the boot time estimator spreadsheet.

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2021.1/Device_Architecture_Tutorials/Versal/Boot_and_Config/vck190_boot_time

2021.1

Fallback & Multiboot

Fallback boot allows Versal Adaptive SoC to automatically boot a different PDI than the initial PDI on the same primary boot device if the first PDI fails to boot.

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2022.1/Device_Architecture_Tutorials/Versal/Boot_and_Config/vck190_fallback

2022.1

Post BootROM State

This Versal example design is intended to illustrate the post bootROM state (pre-PLM) of the device on different boot modes, just to verify the registers modified by Versal ROM code.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_post_boot

2020.2

Boot Files

This blog post provides an overview of the Versal Boot files

VCK190, VMK180, VPK120, VPK180

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/A-Brief-Overview-of-the-Versal-Boot-files/ba-p/1146981

2020.2

USB Secondary Boot Mode

In this blog entry we will demonstrate how to boot Linux from a USB secondary boot

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2022.1/Device_Architecture_Tutorials/Versal/Boot_and_Config/vck190_plm_usb_second

2022.1

JTAG Boot

Vivado in-depth tutorial covering the JTAG boot mode flow

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/master/Device_Architecture_Tutorials/Versal/Boot_and_Config/JTAG_Boot 2020at 2021.2 · Xilinx/Vivado-Design-Tutorials (github.com)

2021.2

OSPI Boot

Example demonstrating octal SPI (OSPI) boot on a VCK190.

VCK190

Vivado-Design-Tutorials/Device_Architecture_Tutorials/Versal/Boot_and_Config/vck190_boot_ospi at 2023.1 · Xilinx/Vivado-Design-Tutorials (github.com)· GitHub

2023.1

PDI Compression

This Versal example design will demonstrate how to generate a compressed and uncompressed PDI for the VCK190.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Boot/tree/master/vck190_boot_compression

2020.2

AXI DMA Standalone application

The Versal example design will show how to run AXI DMA standalone application example on VCK190 and intended to demonstrate the AXI DMA standalone driver which is available as part of the Xilinx Vivado and Vitis.

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/20222023.12/ced/Xilinx/IPI/VCK190-AXIDMA-Example2022

2023.12

CIPS and DDR

Configurable example design showing CIPS IP and DDR connections, delivered via the CED Store for use within Vivado

VCK190/VMK180

https://github.com/Xilinx/XilinxCEDStore/tree/2022.1/ced/Xilinx/IPI/cips_ddr_pl_debug

2022.1

CIPS VIP

Configurable example design showing simulating with the CIPS Verification IP, delivered via the CED Store for use within Vivado

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/2022.1/ced/Xilinx/IPI/cips_vip

2022.1

AXI BRAM

This Blog entry is intended to illustrate how to access the AXI BRAM from the Versal™ Application processing Unit (APU) through the NoC

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Basic-read-write-to-AXI-BRAM-from-PS-APU-through-NoC-in-Versal/ba-p/1172775

2020.2

CIPS & MicroBlaze

This blog post shows how to leverage Versal CIPS IP from MicroBlaze

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/How-to-leverage-Versal-CIPS-IP-from-MicroBlaze/ba-p/1184023

2020.2

Memory Interfaces

This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal Adaptive SoC devices. 

VCK190, VMK180, VPK120, VPK180

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Getting-Started-with-Versal-Memory-Interfaces/ba-p/1192335

2020.2

NoC and DDRMC

This example connects many different DDR devices simultaneously in one design to communicate to PS through NoC. It connects one DDR4 device and two interleaved LPDDR4 devices, which requires one NoC instance to configure the DDRMC for the DDR4 device and another NoC instance to configure the two interleaved DDRMCs for the two LPDDR4 devices.

VCK190/VMK180

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/03-Multiple_DDRMC

2021.1

NoC and DDRMC

This tutorial introduces the basic concepts, tools, and techniques of the NoC and DDR memory controller design flow in Vivado

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Intro_Design_Flow

2021.1

NoC and DDRMC

Learn how to tune your NoC and DDR memory controller designs to deliver optimum performance for your designs.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Performance_Tuning

2021.1

NoC

This tutorial uses a complex design example to demonstrate how the NoC simplifies the design process for on-chip data movement.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/04-NoC_Data_Movement_Comparison

2021.1

PCB Design DDRMC

This tutorial introduces best pracices for working with DDR memory pinouts in Versal.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/PCB_Design/Memory_Pinouts

2020.2

PCB Design DDR

This tutorial covers how to perform DDRx signal integrity simulations with the Mentor Graphics DDRx Wizard.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/PCB_Design/Hyperlynx_DDRx_Timing_Models

2020.2

DDR Calibration Done

This blog post shows how to export the DDR Calibration done pin to the PL in Versal.

VCK190, VMK180, VPK120, VPK180

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-How-to-export-the-DDR-Calibration-done-pin-to-the-PL/ba-p/1230598

2020.2

Performance AXI Traffic Generator

Introduction to the simulation-only and synthesizable versions of the Versal Performance Traffic Generator.

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2022.1/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Versal_Performance_AXI_Traffic_Generator

2022.1

Versal Cache Coherency

Demonstrates how to perform cache coherent transactions from different masters connected to the CCI-500 or cache coherent interconnect on a Versal device.

VCK190

Versal Cache Coherency

2022.2

PS-GEM

This blog demonstrates how to bring up the PS-GEM in Versal.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet/tree/master/2021.1/ps_mio_eth_1g_prod

2021.1

PS and PL based Ethernet

Example designs of using PS GEM and PL BASE-X or SGMII IP on PL with 1G SFP.

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet/tree/master/2022.1/ps_emio_basex_1g

2021.1

PL 1G Ethernet

This project is about building Versal based AXI 1G/2.5G Ethernet Subsystem example design and testing it by targeting on VCK190 Adaptive SoC device using SGMII SFP

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet/tree/master/2020.2/pl_eth_1G

2020.2

MRMAC

This blog covers the key differences between designing with UltraScale+ CMAC and Versal MRMAC.

VCK190, VMK180, VPK120, VPK180, VHK158

https://support.xilinx.com/s/article/1209580

2020.2

 MRMACMRMAC

MRMAC Ethernet TRD with 1588 PTP PPS Phase Synchronization feature and Inline Timestamping logic

 VCK190

https://github.com/Xilinx/vck190-ethernet-trd

 2022.2

DCMAC

 DCMAC even or odd active lane selection when GTM line rate is 106.25 Gb/s.

N/A

https://support.xilinx.com/s/article/Using-even-or-odd-active-lanes-when-DCMAC-line-rate-is-106-25-Gb-s?language=en_US

2023.1

DCMAC

Versal DCMAC example design running on NoC DDRMC LPDDR4

N/A

 https://support.xilinx.com/s/article/Versal-DCMAC-example-design-running-on-NOC-DDRMC-LPDDR4?language=en_US

2023.1