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Component Name

Platform/SoC Supported

Bug Description


Document update

  • Updated the MAC address priority

  • Fixed DFX section documentation

  • Changed the ATF terminology to TF-A terminology

  • Fixed fpga-manager template section documentation


  • MicroBlaze

  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Fixed openamp-fw-echo-test build failure in template flow

  • In DFX flow, device tree includes for the PL are in the wrong order so the device tree does not compile. Fixed the order

  • Creating ZynqMP design with AXI EMMC in PetaLinux is not configured successfully. Fixed the issue.

  • Fixed Qt5 build failure with petalinux-build --sdk

  • Fixed FSBL compiler flag not working through petalinux-config issue.

  • Fixed QEMU boot issue for VCK5000

  • Fixed PetaLinux Kernel Configuration applies default configuration after saving the configuration issue.

Linux Kernel and Drivers

  • MicroBlaze

  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Linux

    • Fixed MACB driver to request firmware dynamic configuration only when a supported PS SGMII interface is present

    • Sync ZDMA coherent and buffer memory masks to 44 bit

    • Fixed an issue with Zynq FPGA manger in programming the bitstream with latest Kernel of 6.1

    • Fixed an issue in USB dwc3 gadget to avoid unwanted error of "IRQ hiber not found" on Versal.

    • Fixed an issue with Zynq UltraScale+ USB during suspend resume when USB is not a wakeup source.

    • Fixed Versal OSPI read timeout issue with higher data size

    • Fixed QSPI flash protect lock/unlock issues with different parts

    • Fixed WWDT timeout issue with a different clock frequency

    • Fixed Versal Linux boot issue without clk_ignore_unused boot argument 

    • Fixed Versal OSPI UBIF's file system boot issue

    • Fixed clk-wizard driver failure with error -22

    • TRNG: Fixed RGRG sequence and bug in pattern check comparison

    • TRNG: Clear schedule array after DF operation is done

BSP, Drivers and Libraries

  • MicroBlaze

  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Baremetal

    • Fixed AXI Ethernet driver Tcl to support detection of connected DMAs/FIFOs when multiple peripherals are connected

    • Fixed an issue in A72 GIC driver to not to enable group0 interrupts while running EL1 NS.

    • Updated EEMI API IDs for PM_FPGA_GET_VERSION and PM_FPGA_GET_FEATURE_LIST across the stack (ATF, PMUFW and Linux) to avoid conflict with other EEMI IDs on Versal.

    • Fixed an issue in MicroBlaze FreeRTOS port due to missing memory barrier in MicroBlaze port.

    • Fixed an issue in FreeRTOS ports for Zynq, Zynq UltraScale+ MPSoC and MicroBlaze in configuring the tick rate.

    • Fixed an issue with CPU driver Tcl to copy proper libraries when FPU is enabled

    • Fixed intc driver and MicroBlaze FreeRTOS port, to fix warnings reported with -Wundef compilation flag.

    • Fixed AXI QSPI data corruption in interrupt mode with TX HALF EMPTY flags

    • Added APIs for resetting the RX and TX buffers in UARTPSV driver

Trusted Firmware-A(TF-A) (old name Arm Trusted Firmware (ATF))

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • ZynqMP

    • Added bitmask for get_op_char API 

    • Panic w/o handoff structure in JTAG 

    • Check smc_fid 23:16 bits 

    • Separated EM from PM SMCs 

    • Fixed bl31_zynqmp_setup.c coding style 

    • Updated the conflicting EEMI API IDs 

    • With DEBUG=1 move bl31 to DDR range 

    • Updated MAX_XLAT_TABLES for DDR memory range 

    • Fixed DT reserved allocated size 

    • Enabled A53 workaround (errata 1530924)

  • Versal

    • Checks smc_fid 23:16 bits 

    • Fixed incorrect regbase for PMC IPI 

    • Syncs location based on IPI_ID macros 

    • Prints proper ATF handoff source 


  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Versal Net

U-Boot upgraded to mainline 2023.01

  • ZynqMP

    • Added display driver for U-Boot console.

  • Versal

    • Added support for OSPI DDR for Micron flashes.

    • Added support for ADI PHY in ethernet.

Device-tree Generation (DTG)

  • MicroBlaze

  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Fixed device tree compilations issue when adding interrupts in design.

  • Fixed incorrect CPU number issue when there are cascaded processors (MicroBlaze +A53/A72) in hw_design "update_cpu_node"

  • Fixed kernel panic issues with dynamic loading of interrupt-controller.

  • Fixed sysmon0 node detection issue even if it was enabled in design


  • MicroBlaze

  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Zynq 7000: Correct ARM core MIDR register

  • ZynqMP: Power button corrected for Ultra96 emulation

  • Versal: Correct memory configurations on DDR CH1

  • Intc: arm_gicv3_its: MSI affinity handling corrected

  • Remote-Port: Correct 64 bit accesses from the CPU over the remote port protocol

PLM (Platform Loader and Manager)

  • Versal

  • Versal PLM

    • Fixed LIBS variable in version-less makefile 

    • Fixed APU IPIs warning logic for Versal Net 

    • Increased stack size by 1KB to fix a SSIT feature issue

    • Switches to SSIT events right after initial NoC path is configured 

    • Removed XilSEM dependency for version-less PLM 

  •  XilPLMI

    • Renamed KAT macros

    • Made XPlmi_SoftResetHandler non-static

    • Added invalid Commands handler Logic

    • Updated invalid node id logic

    • Clears SSS CFG Error after configuring SSS for SBI to DMA for Versal Net

    • Added Null to invalid command handler of XilPLMI error module

    • Timeout Settings info added for JTAG_SBI

    • Added support for SSIT Single EAM Event forwarding from Secondary SLRs

    • Initialized subsystem ID of CDO command for proc

    • Only resets UART_INITIALIZED while processing tamper response

    • Added PCR Log update event for PCR log notification

    • Removed Triggering of SSIT ERR2 from Secondary SLR to Primary SLR

    • Created Secure Lockdown as a Critical Priority Task

    • Clears End Stack before processing any CDO partition

    • Handles SSIT Events from PPU1 IRQ directly

    • Notifies Other SLRs about Secure Lockdown

    • Removed usage of double data type

    • Removed bypassing of PLM Set Alive during boot

    • Added support to update crypto status in RTCA

    • Fixed CFI readback logic for Versal Net

    • Added XilSEM SW triggered error events

    • Checks to skip SRST and multiboot register update for Secondary Boot Modes

    • Removed runtime check to validate KAT status

  • XilLoader

    • Used macro for redundancy checks for Xil_SMemCpy

    • Added NULL to invalid Command handler in Xplmi module structure

    • Fixed Subsystem PdiInstance Valid Header

    • Sends Load PDI response in Payload[1]

    • Fixed compilation warning when PLM_SECURE_EXCLUDE is enabled

    • Added End Of PDI SYNC Logic

    • Fixed bug in XLoader_SecureClear

  •  XilPDI

    • Added PcrInfo attribute in XilPdi_ImgHdr

Secure libraries

  • Versal

  • XilSecure

    • Passed AesDmCfg structure as reference instead of value

    • Added NULL to Invalid Command handler logic for XilSecure

    • Fixed print issues in ECDSA examples

    • Added Null to invalid command handler of XXilSecure module

    • Made curve enumerations P384 and P521 visible to customers

    • Fixed compilation error in XilSecure in server mode

    • Added Error code for unaligned data

    • Added an instance for SHA1 engine

    • Added invalid command handler logic

    • Added support for SHA2-384 digest

    • Added support for generation of Ephemeral Key

    • Added API to set or clear KAT mask for external modules

    • AES key clear should be done before AES is set under reset

    • Added support to provide crypto indicator when crypto is in use

    • Initializes Payload to zero and make it volatile

    • Addressed Security review comments

    • Fixed code alignment in ECDSA GenerateSign/VerifySign APIs

    • Corrected the mask for PS_SRST

    • Modified secure environment configuration


    • Added missing Param description for Resource

    • Removed runtime check to validate KAT status

    • Fixed compilation failure when PLM_SECURE_EXCLUDE is enabled

  • XilPUF

    • Removed xilpuf_regeneration_example and xilpuf_regeneration_client_example

    • Added support for ID only regeneration in xilpuf_example and xilpuf_client_example

    • Store PUF Aux after shifting

  • XilNVM

    • Added provisioning support for XilNVM

    • Made Revocation ID 0 as valid

    • Fixed the unaligned data exception while programming PUF

PMUFW (Platform Management Unit Firmware)

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Fix added for issues in FPD power down in secure boot use cases

  • Added EXPORT eFuse check for AES, SHA and RSA IPI calls


  • Updated to give/change permissions for writing another overlay config object

  • Cleanup of dynamic feature config logic to enable them only if dynamic feature config is enabled

  • Added IOCTL support for dynamic SD, GEM and USB configuration under ENABLE_DYNAMIC_MIO_CONFIG macro which is disabled by default

  • Gives an error when the same overlay configuration for an existing node is called multiple times

  • Added provision in ZynqMP PMUFW to skip XFPGA_SECURE_MODE macro

  • Returns unique error code if slave is already configured

  • Added support for feature check API

  • Implemented new APIs to get XilFPGA component information

  • Re-apply PLL workaround when DP device is added

  • Provided user option to manually enable DDR XMPU settings using ENABLE_DDR_XMPU macro which is disabled by default

  • Fixed issue on SOM related to enabling build flags

Zynq UltraScale+ FSBL

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Removed DDR IO retention during boot



  • None

Image Selector, Image Recovery (SOM Kria)

Zynq UltraScale+ MPSoC 

  • imgsel

    • Provided support to build Image selector using Vitis

  • img_rcvry

    • Prevents access to SD card on SOM starter kits

    • Added debug print levels



  • Added XilSEM client support for PL MB and A72 bare metal application users.

  • Added XilSEM client support for At2 Linux application users

    • Added API ID feature check

  • Added Run-time check for number of SLRs present in a device instead of using a fixed macro

  • Support for tandem designs

  • Support for new SSIT (H20, H40, H20_H4, H30_H8) devices

  • Support for new mono (VM1502.& VM1402) devices


  • MicroBlaze

  • Zynq 7000

  • Zynq UltraScale+ MPSoC

  • Zynq UltraScale+ RFSoC

  • Versal

  • Fixed xilinx-bootbin recipe with Versal Net arch option for packaging Versal Net device boot.bin

  • Fixed README with proper Yocto Project docs link in meta-xilinx layer.

  • Added boot.bin for zynqmp-generic wic image.

  • Fixed incorrect append operation in u-boot-xlnx-uenv recipe.

  • Fixed license QA Issues in platform-init recipe.

  • Replaced ABORT keyword with HALT in local.conf.sample file

  • Removed xlnxvideoscale support in gstreamer-plugins-bad recipe.

  • Removed meta-python2 dependencies in meta-jupyter README.

AIE Driver


  • Enhanced error messages when standard Linux operations fail