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This page provides detailed information related to Design Module 13 - Xilinx Low Latency HLG SDI Audio Video Capture and Display with PL DDR.

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  • Interlaced and Fractional pipelines are not supported with LLP2.

√ - Supported
x – Not supported

The below table gives information about the features supported in this design. 

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In a typical computer, there are many sources that can be used as a time source, e.g., the system time, sound cards, CPU performance counters, etc. For this reason, GStreamer has many GstClock implementations available. Note that clock time doesn't does not have to start from 0 or any other known value. Some clocks start counting from particular start date, others from the last reboot, etc.

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When the pipeline goes to the PLAYING state, it will go over all elements in the pipeline from sink to source and ask each element if they can provide a clock. The last element that can provide a clock will be used as the clock provider in the pipeline. This algorithm prefers a clock from an audio sink in a typical playback pipeline and a clock from source elements in a typical capture pipeline.

There exist some Some bus messages exist to let you know about the clock and clock providers in the pipeline. You can see what clock is selected in the pipeline by looking at the NEW_CLOCK message on the bus. When a clock provider is removed from the pipeline, a CLOCK_LOST message is posted and the application should go to PAUSED and back to PLAYING to select a new clock.

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