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This page provides all the information related to Design Module 12 - VCU TRD Xilinx low latency (LLP2) PL DDR HDMI Video Capture and Display design.

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Pixel Format

GStreamer Format

Media Bus Format

GStreamer HEVC Profile

GStreamer AVC Profile

Kmssink Plane-id

XV20

NV16_10LE32

UYVY10_1X20

main-422-10

high-4:2:2

34 and 35

NV16

NV16

UYVY8_1X16

main-422

high-4:2:2

36 and 37

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