Time-Sensitive Networking (TSN) is a set of standards under development by the Time-Sensitive Networking task group of the IEEE 802.1 working group.
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TSN user space utilities and sample configurations are provided to enable TSN functionality. Please refer to the TSN SW user guide and the following sections for more details.
Kernel Configuration
The following config options should be enabled in order to build the TSN Subsystem:
CONFIG_XILINX_TSN
CONFIG_AXIENET_HAS_TADMA
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Please refer to PL Ethernet and DMA documentation for additional information: Documentation/devicetree/bindings/net/xilinx_axienet.txt
For more details on phy bindings please refer "Documentation/devicetree/bindings/net/phy.txt"
TSN System
- Xilinx’s TSN IP Switch has three ports Endpoint (Port 0), MAC1 (Port 1) and MAC2 (Port 2)
- Endpoint is connected to MCDMA (Multichannel DMA), each MCDMA channel is a dedicated channel for each type of traffic, i.e. Best Effort, Scheduled Traffic and Reserved. There could be other use cases where there would be separate channels for management traffic
- MAC1 is connected to external world by PHY1
- MAC2 is connected to external world by PHY2
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c. 802.1ASREV (not all features may be available. See ptp4l/openAvnu documentation).
PTP offload on R5 in zynqmp
Xilinx TSN solution offers running multiple instances of 802.1AS PTP function(ptp4l) on RPU of zyng Ultrascale platform. This is implemented by porting PTP(ptp4l) daemon and part of TSN IP driver to FreeRTOS running on R5. The control path is handled through A53(main processor), through OpenAMP frame-work.
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Running gPTP(802.1AS):
gPTP daemon can be run in two ways. One way is to run it from OpenAvnu, and the other is to run it from ptp4linux. Latter is preferred as it prints rms values at slave to identify sync with master.
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You would observe that every second 12 ST packets are sent of which 8 packets are sent in the 100us of 10 ms cycle and the rest 4 packets are sent in the next cycle.
As we can see in the above picture, from 4th packet until 11th packet (8 packets) are received sequentially and the next packet starts after 10ms delay (packet no. 12).
Running IPIC:
IP interception translates the transmit packet with the configured source, destination MAC addresses, VLAN ID and PCP values if the packets' IPv4 tuples (source IP, destination IP, DSCP, protocol, source port number and destination port number) match. IPIC module maintains hash entries of IPv4 tuples and if the out-going packets' tuple data match with that of hash entries , translates the IP stream.
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