Versions Compared

Old Version 22

changes.mady.by.user Sunil Vaghela

Saved on

compared with

New Version Current

changes.mady.by.user Sunil Vaghela

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

This page provides all the information related to Design Module 12 - VCU TRD Xilinx low latency(LLP2) PL DDR HDMI Video Capture and Display design.

...

Pixel Format

GStreamer Format

Media Bus Format

GStreamer HEVC Profile

GStreamer AVC Profile

Kmssink Plane-id

XV20

NV16_10LE32

UYVY10_1X20

main-422-10

high-4:2:2

34 and 35

NV16

NV16

UYVY8_1X16

main-422

high-4:2:2

36 and 37

  • Video0 in the each gst-launch pipelines indicates a video node for the input source.

  • Make sure HDMI-Rx should be configured to 4kp60 mode, while running below example pipelines.

  • LLP1/LLP2 stream-in pipelines are not supported using vcu_gst_app.

  • For LLP1/LLP2 Multi-stream HEVC serial and stream-out use-cases (2-4kp30, 2-1080p60, 4-1080p60), use ENC_EXTRA_OP_BUFFERS=10 variable before gst-launch-1.0 command.

  • For LLP1/LLP2 Multi-stream serial and stream-in use-cases (2-4kp30, 2-1080p60, 4-1080p60), use internal-entropy-buffers=3 property in decoder.For NV16 use-cases, please change the value of the plane-id.

Run the following gst-launch-1.0 command to display XV20 video on HDMI-Tx using low-latency (LLP1) GStreamer pipeline.

...