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This page provides detailed information related to Design Module 13 - Xilinx Low Latency HLG SDI Audio Video Capture and Display with PL DDR.


  • Interlaced and Fractional pipelines are not supported with LLP2.

√ - Supported
x – Not supported

The below table gives information about the features supported in this design. 


2.3 Optimum VCU Encoder parameters for use-cases: