This page provides detailed information related to Design Module 13 - Xilinx Low Latency HLG SDI Audio Video Capture and Display with PL DDR.
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Interlaced and Fractional pipelines are not supported with LLP2.
√ - Supported
x – Not supported
The below table gives information about the features supported in this design.
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For PetaLinux related limitations please refer to: PetaLinux 2022.1 - Product Update Release Notes and Known Issues
For VCU related limitations please refer to Answer Record 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues , Xilinx Zynq UltraScale+ MPSoC Video Codec Unitand PG252 [TODO: To be updated by 4th May, 2022].
2.3 Optimum VCU Encoder parameters for use-cases:
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