This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE ™ IP AXI Performance Monitor (axi
performance monitor driver which is available as part of the Xilinx Vivado and SDK distribution_perf_mon) soft IP
Table of Contents
| Table of Contents | ||||
|---|---|---|---|---|
|
AXI Performance Monitor has the capability to measure major performance metrics (for AXI4, AXI4-Lite or AXI4-Stream based systems) such as bus latency for specific master/slave, amount of memory traffic for specific duration etc.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| ospipsvaxipmon | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axipmon | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axipmon |
| Info |
|---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axipmon |
The driver source code is organized into different folders. The table below shows the ospipsv axipmon driver source organization.
| Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and .mdd fileyaml files |
examples | Example applications that show how to use the driver features |
| src | Driver source files make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer TRM
Features
- Software triggered IO mode (STIG) up to 8-bytes of data transfers.
- Indirect DMA reads.
- Local SRAM to reduce AHB overhead.
- Supports SDR and DDR protocols.
- Programmable master mode clock frequencies.
- Programmable peripheral selects (chip select).
- Support for Single and Octal instructions.
- Interrupts and polled based operations.
Known Issues and Limitations
- Macronix flash works only up to 150MHz.
...
Known Issues/Limitations
- None
Change log
2023.2
2023.1
- None
2022.2
- None
2022.2
- None
2021.2
- None
2021.1
- None
2020.2
2020.1
- None
2019.2
- None
2019.1
- None
2018.3
...