This page gives an overview of the bare-metal driver support for the PS CAN.
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Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver name | Path in Vitis | Path in Github |
|---|---|---|
| canps | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/canps | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/canps |
| Info |
|---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/canps |
The driver source code is organized into different folders. The table below shows the canps driver source organization.
| Directory | Description |
|---|---|
| src | Driver source files, make and cmakelists file |
| examples | Example applications that show how to use the driver features |
| doc | Provides the API and data structure details |
| data | Driver .tcl, .yaml and .mdd file |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder)
and CMakeListsand CMakeLists.txt(in src folder) files
would be used inare needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer Chapter 20: Can Controller in Zynqmp Trm
Features
Controller Features:
- Compatible with the ISO 11898 -1, CAN 2.0A, and CAN 2.0B standards
- Standard (11-bit identifier) and extended (29-bit identifier) frames
- Bit rates up to 1 Mb/s
- Transmit message FIFO (TxFIFO) with a depth of 64 messages
- Transmit prioritization through one high-priority transmit buffer (TxHPB
- Watermark interrupts for TxFIFO and RxFIFO
- Automatic re-transmission on errors or arbitration loss in normal mode
- Receive message FIFO (RxFIFO) with a depth of 64 messages
- Four Rx acceptance filters with enables, masks and IDs
- Loop back and snoop modes for diagnostic applications
- Mask able error and status interrupts
- 16-Bit time stamping for receive message
- Readable Rx/Tx error counters
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