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connect
fpga -no-rev -f design_1_wrapper/hw/design_1_wrapper.bit
# Download FSBL to A9 #0
targets -set -nocase -filter {name =~ "APU"}
source design_1_wrapper/hw/ps7_init.tcl;ps7_post_config
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}
dow design_1_wrapper/zynq_fsbl/fsbl.elf
con
after 500
stop
dow hello_world_mb/Debug/mb_bootloop_le.elf
# set stdin/out to mdm in BSP settings
#targets -set -filter {name =~ "MicroBlaze Debug Module at USER2"}
#jtagterminal
# Wake up Microblaze
targets -set -nocase -filter {name =~ "APU"}
mwr -force 0xE000A284 0x00000001
mwr -force 0xE000A048 0x00000001 |
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The mb_bootloop_le.elf can be copied from your Vivado project; project_1.gen\sources_1\bd\design_1\ip\design_1_microblaze_0_0\data |
I then launch Vitis, and created a Debug Configuration. In the Target setup and removed all the init (as this is done via the script):
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