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Table of Contents
Table of Contents

Document History

DateVersionAuthorDescription of Revisions
05/12/20161.0Rutuja Chavan & Rajesh GugulothuInitial Version
17/02/20171.1Rutuja Chavan1. Updated to 2016.4 tool version
2. Designed for ZCU102 Rev1.0 and RevB/C/D Boards
16/05/20172.0Rajesh Gugulothu1. Updated to 2017.1 tool version
2. Designed for ZCU102 Rev1.0 and RevB/C/D prod silicon Boards
11/06/20182.1Surender Polsani1. Updated to 2018.1 tool version
2. Designed for ZCU102 Rev1.0 and RevB/C/D prod silicon Boards


The Zynq® UltraScale+™ MPSoC USB 3.0 controller consists of two independent dual-role device (DRD) controllers. Both can be individually configured to work as host or device at any given time. The USB 3.0 DRD controller provides an eXtensible host controller interface (xHCI) to the system software through the advanced eXtensible interface (AXI) slave interface. An internal DMA engine is present in the controller and it utilizes the AXI master interface to transfer data. There are four primary types of communication defined by the USB protocol, based on which any required application can be built without changing the firmware or underlying hardware for different applications. These transfer types are Control Transfer, Bulk Transfer, Isochronous transfer and Interrupt transfer. Zynq® UltraScale+™ MPSoC USB3.0 controller supports all four types of transfers.This Tech Tip explains how to enable all the configuration options, step by step procedure to use the Zynq® UltraScale+™ MPSoC USB 3.0 controller in device mode and make use of bulk transfer type for mass storage device using the USB 3.0. For complete specifications of USB protocol and class specific specifications refer:
This design covers:

  • The USB mass storage device example block diagram and overview
  • How to configure all the Zynq® ultrascale +™ MPSoC Linux kernel and dependent files for the mass storage class reference2-16
  • Setup to test Zynq® UltraScale+™ MPSoC USB 3.0 mass storage class functionality with Windows as well as Linux host machine


Implementation Details
Design TypePS Only
SW TypeZynq® UltraScale+™ MPSoC Linux
CPUsARM Cortex A53 Core 0 running at 1.1 GHz
PS Features
  • DDR3
  • Cache
  • L1 and L2 Cache
  • OCM
  • Generic Interrupt Controller
  • USB 3.0 Controller
Boards/ToolsZCU102 Prod silicon Boards (B/C/D)
ZCU102 Rev 1.0 Board
Xilinx Tools VersionXilinx petalinux SDK 2018.1 or latest
Other Details--