This page gives an overview of Zynqmp/ Versal OCM EDAC driver which is available in Xilinx Linux distribution as drivers/edac/zynqmp_ocm_edac.c

Overview

The on-chip memory (OCM) module contains 256 KB of RAM. It supports a 128-bit AXI slave interface port. The OCM has eight exclusive access monitors that
allow the OCM to simultaneously monitor up to eight exclusive access transactions. The OCM supports high AXI read and write throughput for RAM access by
implementing the RAM as a double-width memory (256 bits). The OCM implements double-width memory to maximize the read and write bandwidth. Maximum
bandwidth is achieved when the read/write accesses are a multiple of 256 bits with 256-bit aligned addresses. The Xilinx memory protection unit (XMPU) is
supported at 4KB memory granularity. The entire 256 KB of RAM can be divided into 64 blocks (4KB each), and assigned security attributes independently.
Arbitration between the read and write channels of the OCM switch ports is performed within the OCM module. OCM supports a 64-bit ECC.

HW/IP Features

• supports a 64-bit ECC
• Single bit error detection and correction
• Double bit error detection
• Error injection support

Driver Features

• Detects and reports the errors on OCM
• Supports error injection for both countable and uncountable errors

Missing features, Known Issues and Limitations

• NA

Kernel Configuration

The following config options should be enabled in order to build ZynqMP OCM EDAC driver:

Code Block
theme Midnight
config EDAC_ZYNQMP_OCM tristate "Xilinx ZynqMP OCM controller" depends on EDAC_MM_EDAC && ARM64 help Support for error detection and correction on the Xilinx ZynqMP OCM controller.

Devicetree Settings

Example:

Code Block
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ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; };

Mainline Status

mainlined

Testing Procedure

The general guideline is that the user chooses an address for testing that is not used by the system.