This page provides an introduction to the "Accelerated Image Classification via Binary Neural Network" (short AIC) design example.
Table of Contents
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Document History
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| Date | Version |
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Document History
| Date | Version | Author | Description of Revisions | |
| 2018-03-26 | V0.1 | Andreas Schuler (MLE) | Initial Document | |
| 2018-04-30 | V1.0 | Andreas Schuler (MLE) | first release | |
| 2018-05-03 | V1.1 | Andreas Schuler (MLE) | Add reference to Xilinx Research Lab | |
| 2018-12-14 | V1.1 | Andreas Schuler (MLE) | Update Document to latest changesAuthor | Description of Revisions |
| 2018-03-26 | V0.1 | Andreas Schuler (MLE) | Initial Document | |
| 2018-04-30 | V1.0 | Andreas Schuler (MLE) | first release | |
| 2018-05-03 | V1.1 | Andreas Schuler (MLE) | Add reference to Xilinx Research Lab | |
| 2018-12-14 | V1.1 | Andreas Schuler (MLE) | Update Document to latest changes |
Introduction
This design example demonstrates how moving software implemented neural networks can be dramatically accelerated via Programmable Logic. In this design a Binary Neural Network (BNN) is implemented. Depending on silicon platform an acceleration of 6,000 to 8,000 times is demonstrated. Via the graphical user interface the user can see metrics, images and classification results.
The work is based on top of the work of the Xilinx Research Lab. More information can be found here:
Inference of quantized neural networks on heterogeneous all-programmable devices (DATE 2018)
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference (FPGA 2017)
Scaling Binarized Neural Networks on Reconfigurable Logic (PARMA-DITAM 2017)
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic (ICCD 2017)
You can also checkout following repositories:
https://github.com/Xilinx/BNN-PYNQ
https://github.com/Xilinx/QNN-MO-PYNQ
For any questions please contact Missing Link Electronics (MLE).
The AIC Demo is available for following Platforms:
| Board | Device | Revision |
| ZCU102 | XCZU9EG | Rev D2, Rev 1.0, Rev 1.1 |
| Ultra96 | XCZU3EG | V1 |
Implementation
| Implementation Details | |
| Design Type | PS & PL |
| SW Type | PetaLinux/Ubuntu, QT5.4.2, OpenCV-3.3.0 |
| CPUs | Quad A53 |
| PS Features | DDR, GPU, Mali400 |
| PL Cores | HLS BNN IP |
| Boards/Tools | ZCU102 or Ultra96, USB Hub, Mouse, Logitech HD Pro Webcam Brio/C920/C525/C615, UHD or HD DisplayPort Monitor |
| Xilinx Tools Version | Vivado 2017.3 |
| Other Details | Vivado Base |
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In the folder aic/src_sw/<platform name>-petalinux all files to rebuild the BOOT.BIN file of the linux system can be found. This is needed if the FPGA design was modified and it is needed to deploy the rebuilt bitstream to the system.
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Bring up the system and run the design
This section describes how to set up the board and peripherals, then explains how to
run the design. All this is based on the pre built design, that can be found on the provided SD-Card
image. If you would like to modify or rebuild parts of the design, please look at section Rebuild the
Design from source.
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