| Table of Contents |
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Introduction
The Xilfpga XilFPGA library provides an interface to for the Linux or bare-metal users for configuring users to configure the programmable logic (PL) over PCAP from PS. The library is designed for
Zynq® UltraScale+ MPSoC to run on top of Xilinx Xilinx® standalone BSPs. In the most common use case, we expect users to run this library on PMU MicroBlaze
with PMUFW to serve requests from Linux for bitstream programming.
How to enable
xilfpga library can be found atIt acts as a bridge
between the user application and the PL device. It provides the required functionality to the user application for configuring the PL device with the required bitstream.
Library Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Library Name | Path in Vitis | Path in Github |
|---|---|---|
| Xilfpga | <Vitis Install Directory>/data/embedded/lib/sw_services/xilfpga_v6_5 | https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilfpga |
...
The driver source code is organized into different folders. The table below shows the axidma driver source organization.
| Directory | Description |
|---|---|
| Doc | Provides the API and data structure details |
...
HW IP Features
- Full Bitstream and Partial Bitstream loading
- Encrypted and Authenticated Full/Partial Bitstream loading
- Readback of Configuration Registers
- Readback of Bitstream(Configuration Data)
- Compressed Bitstream
Features supported in the driver
- Full Bitstream Support
- Non Secure Bitstream
- Encrypted Bitstream
- Authenticated Bitstream
- Authenticated and Encrypted Bitstream
- Compressed Bitstream
- Partial Bitstream Support that doesn't require PL drivers
- Non Secure Partial Bitstream
- Encrypted Partial Bitstream
- Authenticated Partial Bitstream
- Authenticated and Encrypted Partial Bitstream
- Readback
- Configuration Registers Readback
- Configuration Data Readback
| data | Library .tcl, .mld and .yaml file |
| examples | Example applications that show how to use the driver features |
| src | Library source files |
Note: The .yaml(in data folder) and CMakeLists.txt(in src folder) files would be used in the System Device-tree based flow.
Library Implementation
For a full list of features supported by this library, please refer to the xilfpga Doc
Features
The following features are supported in Zynq UltraScale+ MPSoC platform:
- Full bitstream loading
- Partial bitstream loading
- Encrypted bitstream loading
- Authenticated bitstream loading
- Authenticated and encrypted bitstream loading
- Readback of configuration registers
- Readback of configuration data
The following features are supported in Versal platform:
- Full/Partial bitstream loading
- Device Key Encrypted bitstream loading
- Authenticated bitstream loading
- Authenticated and Device-key encrypted bitstream loading
Known Issues and Limitations
Test Cases
There are examples which will illustrate the xilfpga usage. They can be found at
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver.
Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.
These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilfpga/examples
ChangeLog
- Added new xilfpga library.
- Added PL power-up and Isolation sequence to the xilfpga library.
- Added PS-PL Reset sequence.
- Added Preprocessor check for XPAR_NUM_FABRIC_RESETS to avoid the compilation errors.
- Added gpio assert logic to properly reset the PL from PS.
- Xilfpga: Fix the check logic issue in xilfpga library
- Updated the source files to updated addtogroup version numbers
- Xilfpga: Remove Authenticated BitStream Loading support from xilfpga library.
- None.
- Xilfpga: Fix Documentation style issues
- Xilfpga: Adds support to Re-validated the user Crypto flags with Image crypto operations
- Xilfpga: Adds Partial Bitstream loading support to the xilfpga library
- xilfpga: Update the Doxygen comments for the recent changes
- xilfpga: Fix issues with Aes user-key cleaning logic
- xilfpga: Fix misra-c required standard violations
- lib: xilfpga: Improve bitstream size handling in the library
- lib: xilfpga: Fix issues with secure partial bitstream loading
- lib: xilfpga: Return proper status in case of secure bitstream passed with nonsecure flags
- lib: xilfpga: Add support for unaligned bitstream
- xilfpga: Fix cpp check warnings
- xilfpga: Fix standalone coding style issues.
- Xilfpga: Modified the PL data handling Logic to support different PL programming interfaces
- xilfpga: Fix typo errors in the library.
- lib: xilfpga: Use XCsuDma_WaitForDoneTimeout() API instead of XCsuDma_WaitForDone()
- xilfpga: Add example for loading partial bitstream
- xilfpga: Fix xilsecure dependencies
- xilfpga: Change the function name as per the standalone drivers standards
- xilfpga: Adds support to load vivado generated .bit and .bin files
- xilfpga: Fix issues with readback
- xilfpga: Add example for readback of configuration data
- xilfpga: zynqmp: Add support for readback of configuration data
- xilfpga: Enhance the ConfigReg readback changes
- Xilfpga: Adding Device Key support with user configuration.
- Xilfpga : Adds Debug prints and New Error codes handling mechanism to the library
- xilfpga: Move flags related macro's from xilfpga_pcap.c to xilfpga.h
- xilfpga: Updated the examples to the new API's
- Xilfpga: Refactoring the xilfpga library to support different PL programming interfaces.
- Xilfpga: Adds Partial Bistream loading support to the xilfpga library
- Xilfpga: Adds support to Re-validated the user Crypto flags with Image crypto operations
- Generated Doxygen documentation and PDF's for sw_services
- xilfpga: Fixed IAR compiler warnings in read back examples
- xilfpga:src:MISRA-C:No brackets to loop body.
- sw_services :xilfpga: Add error recovery mechanism to xilfpga
- xilfpga: update the data handling logic.
- lib: xilfpga: Update the examples for the latest xilfpga version
- Xilfpga: Updated Makefile to support IAR
- lib: xilfpga: Adds missing extern protection macros
- Published xilfpga PDF document
- Xilfpga: Improve error handling in the bitstream validation path.
- Xilfpga: Fix issues with Initialize empty status
- xilfpga: Fix for Secure Header Zeroize issue
- Xilfpga: Adds support to clear out the SHA3 engine.
- xilfpga: Update documentation for readback API's
| Test Name | Example Source | Description |
|---|---|---|
| Full Bitstream/PDI loading | xfpga_load_bitstream_example.c | Transfer the user provided Full Reconfiguration Bitstream into the PL. |
| Partial Bitstream/PDI loading | xfpga_partialbitstream_load_example.c | Transfer the user provided Partial Reconfiguration Bitstream into the PL region |
Readback of configuration registers | xfpga_reg_readback_example.c | This example prints out the values of all the configuration registers related to FPGA |
Readback of configuration Data | xfpga_readback_example.c | This example prints out the fpga configuration data |
Example Application Usage
Full Bitstream/PDI loading
Transfer the user provided Full Reconfiguration Bitstream into the PL.
Expected Output
| Code Block | ||
|---|---|---|
| ||
Loading Bitstream for DDR location :0x80000
Trying to configure the PL ......
PL Configuration done successfully |
Partial Bitstream/PDI loading
Transfer the user provided Partial Reconfiguration Bitstream into the PL Region.
Expected Output
| Code Block | ||
|---|---|---|
| ||
Loading Partial Reconfiguration Bitstream from DDR location :0x80000
Trying to configure Partial Reconfiguration Bitstream into the PL ......
Partial Reconfiguration Bitstream loaded into the PL successfully |
Readback of configuration registers
This example prints out the values of all the configuration registers related to FPGA
Expected Output
| Code Block | ||
|---|---|---|
| ||
Register Read back example
Value of the Configuration Registers.
CRC -> 0
FAR -> 7fc0000
FDRI -> 0
FDRO -> effffffe
CMD -> d
CTRL0 -> 101
MASK -> 0
STAT -> 16907ffc
LOUT -> 0
COR0 -> 38003fe5
MFWR -> 0
CBC -> 0
IDCODE -> 1484a093
AXSS -> 0
COR1 -> 400000
WBSTR -> 0
TIMER -> 0
BOOTSTS -> 1
CTRL1 -> 0
Successfully ran Register Read back example |
Readback of configuration Data
This example prints out the fpga configuration data.
Expected Output
| Code Block | ||
|---|---|---|
| ||
FPGA Configuration data Read back example
0000 00000 00000 0000 0000
.... ..... ..... .... ....
.... ..... ..... .... ....
.... ..... .... .... ....
Successfully ran FPGA Configuration Read back example |
Performance
- N/A
ChangeLog
- 2023.1
- 2022.1
- 2022.1
- 2021.2
- 2021.1
- 2020.2
- 2020.1
- 2019.2
- 2019.1
- 2018.3
- 2018.2
- 2018.1
- 2017.4
- 2017.3
- 2017.2
- 2017.1
- 2016.4
- 2016.3