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This page gives an overview of the bare-metal driver support for the PS I2C controller.

Table of Contents

Table of Contents
excludeTable of Contents


The I2C controllers can function as a master or a slave in a multi-master design. They can
operate over a clock frequency range up to 400 kb/s.

Source path for the driver:
Driver source code is organized into different folders. Below diagram shows the iicps driver source organization

-- Doc - Provides the API and data structure details
- Examples - Reference application to show how to use the driver APIs and calling sequence
- Source - Driver source files



The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github


<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/iicps


Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is:

The driver source code is organized into different folders.  The table below shows the ospipsv driver source organization. 



Provides the API and data structure details


Driver .tcl, .yaml and .mdd file


Example applications that show how to use the driver features


Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 69: I2C Controller in Versal TRM


I2C bus specification version 2
Supports 16-byte FIFO
Programmable normal and fast bus data rates

Master mode
Write transfer
Read transfer
Extended address support
Support HOLD for slow processor service
Supports TO interrupt flag to avoid stall condition

Slave monitor mode

Slave mode
Slave transmitter
Slave receiver
Extended address support (10-bit address)
Fully programmable slave response address
Supports HOLD to prevent overflow condition
Supports TO interrupt flag to avoid stall condition

Software can poll for status or function as interrupt-driven device
Programmable interrupt generation