1 Overview

This module enables capture of video from an HDMI Rx subsystem implemented in the PSPL. The video can be displayed through the HDMI Tx subsystem implemented in the PSPL. The module can stream-out and stream-in live captured video frames through an Ethernet interface at ultra-low latencies using Sync IP. This module supports multi-stream for NV12 pixel format.

The VCU encoder and decoder operate in slice mode. An input frame is divided into multiple slices (8 or 16) horizontally. The encoder generates a slice_done interrupt at every end of the slice. Generated NAL unit data can be passed to a downstream element immediately without waiting for the frame_done interrupt. The VCU decoder also starts processing data as soon as one slice of data is ready in its circular buffer instead of waiting for complete frame data. The Sync IP does an AXI transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of granularity at the video buffer level. Sync IP is responsible for synchronizing buffers between Capture DMA and VCU encoder as both work on same buffer.

The capture element (FB write DMA) writes video buffers in raster-scan order. SyncIP monitors the buffer level while the capture element is writing into DRAM and allows the encoder to read input buffer data if the requested data is already written by DMA, otherwise it blocks the encoder until DMA completes its writes. On the decoder side, the VCU decoder writes decoded video buffer data into DRAM in block-raster scan order and displays reads data in raster-scan order. To avoid display under-run problems, software ensures a phase difference of "~frame_period/2", so that decoder is ahead compare to display.

This design supports the following video interfaces:

Sources:

• HDMI-Rx capture pipeline implemented in the PS.
• Stream-In from network or internet.

Sinks:

• HDMI-Tx display pipeline implemented in the PS.

VCU Codec:

• Video Encode/Decode capability using VCU hard block in PS
  • AVC/HEVC encoding
  • Encoder/decoder parameter configuration.

Video format:

• NV12

Supported Resolution:

The table below provides the supported resolution from command line app only in this design.

√ - Supported
NA – Not applicable
x – Not supported

The below table gives information about the features supported in this design. 

The below figure shows the Xilinx Low Latency PS DDR NV12 HDMI design hardware block diagram.

The below figure shows the Xilinx Low Latency PS DDR NV12 HDMI design software block diagram.

1.1 Board Setup

Refer below link for Board Setup

• Zynq UltraScale+ MPSoC VCU TRD 2019.2 Board Setup

• Follow the below steps to switch the HDMI-Rx resolution from 1080p60 to 4kp60.
  • Check current HDMI Input Source Resolution (1080p60) by following the above-mentioned steps.
  • Run vcu_gst_app for current HDMI resolution (1080p60) by executing the following command.

$ vcu_gst_app /media/card/config/input.cfg

Below configurations needs to be set in input.cfg for non-LLP2 HDMI-1080p60 use-case.

Common Configuration    : START
Num Of Input            : 1
Output                  : HDMI
Out Type                : Display
Frame Rate              : 60
Exit

Input Configuration     : START
Input Num               : 1
Input Type              : hdmi_1
Raw                     : FALSE
Width                   : 1920
Height                  : 1080
Format                  : NV12
Enable LLP2             : FALSE
Exit

Encoder Configuration   : START
Encoder Num             : 1
Encoder Name            : HEVC
Profile                 : Main
Rate Control            : Low_Latency
Filler Data             : False
QP                      : Auto
L2 Cache                : TRUE
Latency Mode            : Sub_Frame
Low Bandwidth           : FALSE
Gop Mode                : Basic
Bitrate                 : 25000
B Frames                : 0
Slice                   : 8
GoP Length              : 60
Preset                  : Custom
Exit

• • Change Resolution of HDMI Input Source from 1080p60 to 4kp60 by following below steps.
    • Set the HDMI source resolution to 4kp60 (Homepage → Settings → Display & Sound → Resolution → change to 4kp60).
    • Save the configuration to take place the change.
  • Verify the desired HDMI Input Source Resolution (4kp60) by following the above-mentioned steps.

• If HDMI Tx link-up issue is observed after Linux booting, use the following command to get the blue screen on HDMI-Tx for 4kp60.

% modetest -D a0070000.v_mix -s 35:3840x2160-60@BG24

• The table below lists the parameters of the pixel format.

• Run the following gst-launch-1.0 command to display NV12 video on HDMI-Tx using ultra low-latency(LLP2) GStreamer pipeline (capture → encode → decode → display). Where "video0" indicates a video node for the input source.

$ gst-launch-1.0 v4l2src io-mode=4 device=/dev/video0 ! video/x-raw\(memory:XLNXLL\), width=3840, height=2160, format=NV12, framerate=60/1 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=25000 num-slices=8 control-rate=low-latency prefetch-buffer=TRUE low-bandwidth=false filler-data=0 cpb-size=1000 initial-delay=500 ! video/x-h265, alignment=nal ! queue max-size-buffers=0 ! omxh265dec low-latency=1 ! video/x-raw\(memory:XLNXLL\) ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false video-sink="kmssink bus-id=a0070000.v_mix plane-id=30 max-lateness=5000000 show-preroll-frame=false sync=true" sync=true

• Run the following gst-launch-1.0 command to stream-out NV12 video using ultra low-latency(LLP2) GStreamer pipeline. Where "video0" indicates a video node for the input source.