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The code snippet below provides an example on using the power_up and power_down procs commands provided above (power_cmds.tcl) to power cycle the GPU Pixel Processor PP0 island .

Code Block
languagetcl
xsdb% source power_cmds.tcl
# Get Power Status of all islands
xsdb% rrd pmu_global pwr_state
pwr_state: 00fffcbf
          pl (Bits [23]): 1         fp (Bits [22]): 1       usb1 (Bits [21]): 1
        usb0 (Bits [20]): 1  ocm_bank3 (Bits [19]): 1  ocm_bank2 (Bits [18]): 1
   ocm_bank1 (Bits [17]): 1  ocm_bank0 (Bits [16]): 1      tcm1b (Bits [15]): 1
       tcm1a (Bits [14]): 1      tcm0b (Bits [13]): 1      tcm0a (Bits [12]): 1
        r5_1 (Bits [11]): 1       r5_0 (Bits [10]): 1    l2_bank0 (Bits [7]): 1
          pp1 (Bits [5]): 1         pp0 (Bits [4]): 1       acpu3 (Bits [3]): 1
        acpu2 (Bits [2]): 1       acpu1 (Bits [1]): 1       acpu0 (Bits [0]): 1

# Power down PP0 island
xsdb% power_down PP0
Initiating Power Down Request (Mask: 0x00000010)...Done

# Get the power island status. Notice that PP0 status shows '0' - powered off
xsdb% rrd pmu_global pwr_state
pwr_state: 00fffcaf
          pl (Bits [23]): 1         fp (Bits [22]): 1       usb1 (Bits [21]): 1
        usb0 (Bits [20]): 1  ocm_bank3 (Bits [19]): 1  ocm_bank2 (Bits [18]): 1
   ocm_bank1 (Bits [17]): 1  ocm_bank0 (Bits [16]): 1      tcm1b (Bits [15]): 1
       tcm1a (Bits [14]): 1      tcm0b (Bits [13]): 1      tcm0a (Bits [12]): 1
        r5_1 (Bits [11]): 1       r5_0 (Bits [10]): 1    l2_bank0 (Bits [7]): 1
          pp1 (Bits [5]): 1         pp0 (Bits [4]): 0       acpu3 (Bits [3]): 1
        acpu2 (Bits [2]): 1       acpu1 (Bits [1]): 1       acpu0 (Bits [0]): 1

# Power back the PP0 island
xsdb% power_up PP0
Initiating Power Up Request (Mask: 0x00000010)...Done

# Get the power island status. Notice that PP0 status shows '1' - powewred on
xsdb% rrd pmu_global pwr_state
pwr_state: 00fffcbf
          pl (Bits [23]): 1         fp (Bits [22]): 1       usb1 (Bits [21]): 1
        usb0 (Bits [20]): 1  ocm_bank3 (Bits [19]): 1  ocm_bank2 (Bits [18]): 1
   ocm_bank1 (Bits [17]): 1  ocm_bank0 (Bits [16]): 1      tcm1b (Bits [15]): 1
       tcm1a (Bits [14]): 1      tcm0b (Bits [13]): 1      tcm0a (Bits [12]): 1
        r5_1 (Bits [11]): 1       r5_0 (Bits [10]): 1    l2_bank0 (Bits [7]): 1
          pp1 (Bits [5]): 1         pp0 (Bits [4]): 1       acpu3 (Bits [3]): 1
        acpu2 (Bits [2]): 1       acpu1 (Bits [1]): 1       acpu0 (Bits [0]): 1

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