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This page gives an overview of the bare-metal driver support for the Octal SPI controller.
Table of Contents
Table of Contents | ||
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Introduction
The octal SPI (OSPI) controller can access one or two flash devices using several different methods. The controller is located with the other flash memory controllers in the PMC. The I/O
interface is routed to the PMC MIO pin bank 0. OSPI is commonly used as a boot device. The controller provides multiple ways to read and write the flash memory:
• STIG/PIO read/write (software triggered instruction generator)
• Direct read/write with address remap
• Non-DMA indirect read/write via AXI slave interface
• DMA indirect read using AXI master interface
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Directory | Description |
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doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and .mdd fileyaml files |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in Versal TRM
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- Macronix flash works only up to 150MHz.
Supported Flash vendors
- Micron
- ISSI
- Gigadevice
- Macronix
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
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Example Design Architecture
NA
Performance
At frequency 133.33 MHz
DDR mode:
Read Speed: 253371 KBPS
SDR-PHY mode:
Read Speed: 128849 KBPS
At frequency 33.33 MHz
SDR NON-PHY mode:
Read Speed: 32625 KBPS
Change Log
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L715
2023.1
None
2022.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.2/doc/ChangeLog#L120
2022.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.1/doc/ChangeLog#L64
2021.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.2/doc/ChangeLog#L300
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