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| Table of Contents |
|---|
...
This page gives an overview of ospipsv driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
the bare-metal driver support for the Octal SPI controller.
Table of Contents
| Table of Contents | ||
|---|---|---|
|
Introduction
The octal SPI (OSPI) controller can access one or two flash devices using several different methods. The controller is located with the other flash memory controllers in the PMC. The I/O
interface is routed to the PMC MIO pin bank 0. OSPI is commonly used as a boot device. The controller provides multiple ways to read and write the flash memory:
• STIG/PIO read/write (software triggered instruction generator)
• Direct read/write with address remap
• Non-DMA indirect read/write via AXI slave interface
• DMA indirect read using AXI master interface
For more information, please refer Chapter 73: Octal SPI Controller in Versal TRM which includes links to the official documentation and resource utilization.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| ospipsv | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/ospipsv | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv |
| Info |
|---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/ |
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...
Driver The driver source code is organized into different folders. Below diagram The table below shows the ospipsv driver source organization.
| Directory |
|---|
...
| Description |
|---|
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doc |
...
Provides the API and data structure details |
...
data | Driver .tcl , .mdd and .yaml files |
examples | Example applications that show how to use the driver |
...
Features Supported
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features | |
| src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in Versal TRM
Features
- Software triggered IO mode (STIG) up to 8-bytes of data transfers.
- Indirect DMA reads.
- Local SRAM to reduce AHB overhead.
- Supports SDR and DDR protocols.
- Programmable master mode clock frequencies.Serial clock with programmable polarity.
- Programmable peripheral selects (chip select).
- Support for Single and Octal instructions.
- Interrupts and polled based operations.
Features not supported
...
Known Issues and Limitations
- Macronix flash works only up to 150MHz.
Supported Flash
...
- Micron (512Mb, 1Gb and 2Gb)
...
vendors
- Micron
- ISSI
- Gigadevice
- Macronix
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv/examples
| Test Name | Example Source | Description |
|---|---|---|
| OSPI Polled mode example |
...
| This examples does basic read and write test from the flash device in Polled mode. | |
| OSPI Interrupt mode example |
...
| This examples does basic read and write test from the flash device in Interrupt mode. | |
| OSPI Non-blocking Polled mode example |
...
Output for the above two examples:
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OSPIPSV Flash Polled Example TestFlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0EraseCmd 0xDCWriteCmd: 0x12ReadCmd 0xCCSuccessfully ran OSPIPSV Flash Polled Ex...
OSPIPSV Flash Interrupt Example TestExecuing on the a72FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0EraseCmd 0xDCWriteCmd: 0x12ReadCmd 0xCCSuccessfully ran OSPIPSV Flash Interrupt Example...
OSPIPSV Flash Polled non-blocking read Example TestFlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0EraseCmd 0xDCWriteCmd: 0x12ReadCmd 0xCCSuccessfully ran OSPIPSV Flash non-blocking read Ex...
| This examples does basic read and write test from the flash device in Non-blocking Polled mode. |
Example Application Usage
OSPI Polled mode example
This examples does basic read and write test from the flash device in Polled mode.
Expected Output
OSPI Interrupt mode example
| Code Block |
|---|
OSPIPSV Flash Polled Example Test
FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0
EraseCmd 0xDC
WriteCmd: 0x12
ReadCmd 0xCC
Successfully ran OSPIPSV Flash Polled Ex |
This examples does basic read and write test from the flash device in Interrupt mode.
Expected Output
| Code Block |
|---|
OSPIPSV Flash Interrupt Example Test
Execuing on the a72
FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0
EraseCmd 0xDC
WriteCmd: 0x12
ReadCmd 0xCC
Successfully ran OSPIPSV Flash Interrupt Example |
OSPI Non-blocking Polled mode example
This examples does basic read and write test from the flash device in Non-blocking Polled mode.
Expected Output
| Code Block |
|---|
OSPIPSV Flash Polled non-blocking read Example Test
FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0
EraseCmd 0xDC
WriteCmd: 0x12
ReadCmd 0xCC
Successfully ran OSPIPSV Flash non-blocking read Ex |
Example Design Architecture
NA
Performance
At frequency 133.33 MHz
DDR mode:
Read Speed: 253371 KBPS
SDR-PHY mode:
Read Speed: 128849 KBPS
At frequency 33.33 MHz
SDR NON-PHY mode:
Read Speed: 32625 KBPS
Change Log
2020.2
- 061d258 - Added support for 64-bit address read from 32-bit processor.
- be92f5a - Added support for ISSI and GIGADEVICE parts.
- 4d606c1, 82955b5 - Added support for stacked mode.
2020.1
- 89db8d5 - Added support for RX periodic tuning (provided user API).
- 294fe39 - Added non-blocking DMA transfer support (provided user API's).
- e2ed45a - Added support for DLL Master mode.
2019.2
- 2f1ecdc - Added RX tuning for SDR-PHY and DDR-PHY modes.
- 9abaa2f - Added support for EL1_NS.
- bb7fa4a - Added support for flash device reset.
2019.1
...
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L715
2023.1
None
2022.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.2/doc/ChangeLog#L120
2022.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.1/doc/ChangeLog#L64
2021.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.2/doc/ChangeLog#L300
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L459
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L456
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L78
2019.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L64
2019.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L118
Related Links
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