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Introduction
This page gives an overview of intc driver which is available as part of the Xilinx Vivado and Vitis distribution.
Table of Contents
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Introduction
The LogiCORE™ IP AXI Interrupt Controller (INTC) core receives multiple interrupt inputs from peripheral devices and merges them into an interrupt output to the system processor. The registers used for storing interrupt vector addresses, checking, enabling and acknowledging interrupts are accessed through the AXI4-Lite interface.
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The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
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intc | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/intc | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/intc |
Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/intc |
The driver source code is organized into different folders. The table below shows the intc driver source organization.
Directory | Description |
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doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and . |
yaml files | |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmakelists file |
Note: The .yaml(in data folder) and CMakeLists.txt(in src folder) files would be used in System Device Tree based flow.
Driver Implementation
For a full list of features supported by this IP, please refer AXI interrupt controller product guide
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Links to Examples
Examples path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv/examplesintc
Test Name | Example Source | Description |
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INTC Self test example | This example performs a self-test to ensure that the hardware was built correctly. | |
INTC simulation mode example | This example demonstrates how to use the interrupt controller driver instance and the hardware device. It is designed to | |
INTC low level example | This is an interrupt example which utilizes low level APIs to configure the interrupt in simulation mode |
Example Application Usage
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This example performs a self-test to ensure that the hardware was built correctly.
Expected Output
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Simulation mode example
This example demonstrates triggering of interrupts in simulation mode.
Expected output
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Low level example
This is an interrupt example which utilizes low level APIs to configure the interrupt in simulation mode
Expected output
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Example Design Architecture
NA
Performance
NA
Changelog
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L277
2023.1
None
2022.2
None
2022.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2022.1/doc/ChangeLog#L40
2021.2
None
2021.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L144
2020.2
Updated tcl to support interrupt ID generation for broader range of HW designs
having slice/concat/OR gate combinationsUpdated Makefile for parallel make execution and incremental build support.https://github.com/Xilinx/embeddedsw/blob/release-2020.2/doc/ChangeLog#L622
Related Links
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