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This module enables capture of video from an HDMI-Rx subsystem implemented in the PL. The video can be displayed through the HDMI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface at ultra-low latencies using Sync IP. This module supports multi-stream four video streams using AXI broadcaster at capture side and mixer at display side for XV20 pixel format. In this design PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k @60 FPS.
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For Petalinux related known issues please refer: PetaLinux 2020.2 - Product Update Release Notes and Known Issues
For VCU related known issues please refer AR# 66763: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues and Xilinx Zynq UltraScale+ MPSoC Video Codec Unit.
Design has a negative slack of WNS around -50 ps . However it does not affect the functionality of the design in the long run also and will be fixed in next release.
To reduce performance issues with llp2 4x serial pipelines, please refer to chapter# 40 of Section VI: Appendices for IRQ Balancing scheme in PG252.
For Out of Memory(OOM) killer error on UART console in long run, please refer to AR# 75900: Why do I see out of memory messages in UART console in long run of VCU TRD multi-stream designs?
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