Page Comparison

AXI DMA Standalone application

The Versal example design will show how to run AXI DMA standalone application example on VCK190 and intended to demonstrate the AXI DMA standalone driver which is available as part of the Xilinx Vivado and Vitis.

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/20222023.12/ced/Xilinx/IPI/VCK190-AXIDMA-Example2022

2023.12

CIPS and DDR

Configurable example design showing CIPS IP and DDR connections, delivered via the CED Store for use within Vivado

VCK190/VMK180

https://github.com/Xilinx/XilinxCEDStore/tree/2022.1/ced/Xilinx/IPI/cips_ddr_pl_debug

2022.1

CIPS VIP

Configurable example design showing simulating with the CIPS Verification IP, delivered via the CED Store for use within Vivado

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/2022.1/ced/Xilinx/IPI/cips_vip

2022.1

AXI BRAM

This Blog entry is intended to illustrate how to access the AXI BRAM from the Versal™ Application processing Unit (APU) through the NoC

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Basic-read-write-to-AXI-BRAM-from-PS-APU-through-NoC-in-Versal/ba-p/1172775

2020.2

CIPS & MicroBlaze

This blog post shows how to leverage Versal CIPS IP from MicroBlaze

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/How-to-leverage-Versal-CIPS-IP-from-MicroBlaze/ba-p/1184023

2020.2

Memory Interfaces

This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal Adaptive SoC devices. 

VCK190, VMK180, VPK120, VPK180

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Getting-Started-with-Versal-Memory-Interfaces/ba-p/1192335

2020.2

NoC and DDRMC

This example connects many different DDR devices simultaneously in one design to communicate to PS through NoC. It connects one DDR4 device and two interleaved LPDDR4 devices, which requires one NoC instance to configure the DDRMC for the DDR4 device and another NoC instance to configure the two interleaved DDRMCs for the two LPDDR4 devices.

VCK190/VMK180

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/03-Multiple_DDRMC

2021.1

NoC and DDRMC

This tutorial introduces the basic concepts, tools, and techniques of the NoC and DDR memory controller design flow in Vivado

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Intro_Design_Flow

2021.1

NoC and DDRMC

Learn how to tune your NoC and DDR memory controller designs to deliver optimum performance for your designs.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Performance_Tuning

2021.1

NoC

This tutorial uses a complex design example to demonstrate how the NoC simplifies the design process for on-chip data movement.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/NoC_DDRMC/04-NoC_Data_Movement_Comparison

2021.1

PCB Design DDRMC

This tutorial introduces best pracices for working with DDR memory pinouts in Versal.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/PCB_Design/Memory_Pinouts

2020.2

PCB Design DDR

This tutorial covers how to perform DDRx signal integrity simulations with the Mentor Graphics DDRx Wizard.

VCK190, VMK180, VPK120, VPK180

https://github.com/Xilinx/Vivado-Design-Tutorials/blob/master/Device_Architecture_Tutorials/Versal/PCB_Design/Hyperlynx_DDRx_Timing_Models

2020.2

DDR Calibration Done

This blog post shows how to export the DDR Calibration done pin to the PL in Versal.

VCK190, VMK180, VPK120, VPK180

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-How-to-export-the-DDR-Calibration-done-pin-to-the-PL/ba-p/1230598

2020.2

Performance AXI Traffic Generator

Introduction to the simulation-only and synthesizable versions of the Versal Performance Traffic Generator.

VCK190

https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2022.1/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Versal_Performance_AXI_Traffic_Generator

2022.1

Versal Cache Coherency

Demonstrates how to perform cache coherent transactions from different masters connected to the CCI-500 or cache coherent interconnect on a Versal device.

VCK190

Versal Cache Coherency

2022.2