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For a full list of features supported by this IP, please refer to Axi Quad Spi.
Features
DMA access (aligned address only)
IO access
Configurable clock
Configurable bus width
Interrupts – will be chosen and enabled internally
Known Issues and Limitations
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Example Design Architecture
NA
Performance
Change Log
2023.1
2022.2
None
2022.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L103
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