This page gives an overview of UARTLite BareMetal driver which is available as part of the Xilinx Vivado and SDK distribution.
Table of Contents
| Table of Contents | ||
|---|---|---|
|
Introduction
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite core provides between
UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI interface and also provides
a controller interface for asynchronous serial data transfer. This soft LogiCORE™ IP core is designed to
interface with the AXI4-Lite protocol.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver name | Path in vitis | Path in github |
|---|---|---|
| uartlite | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartlite | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite |
| Info |
|---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartlite |
The driver source code is organized into different folders. The table below shows the uartlite driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
| src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf
Features
• AXI4-Lite interface for register access and data transfers• Full duplex
• 16-character transmit and receive FIFOs
• Configurable number of data bits (5-8) in a character
• Configurable parity bit (odd or even or none)
• Configurable baud rate
Known Issues and Limitations
None
...
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L138
2022.2
None
2022.1
Nonehttps://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L119
2021.2
None
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L483
...