Zynq UltraScale＋ MPSoC VCU TRD 2019.1 - PCIe Transcode

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√ - Supported
NA – Not applicable
x – Not supported

Hardware Overview

This Design uses the PCI Express (PCIe®) Endpoint block in an x4 Gen3 configuration along with DMA/Bridge Subsystem for PCI Express for data transfers between the host system memory and the Endpoint.

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In the system to card direction, the DMA block moves data from the host memory to the PL-side through PCIe and then writes the data to PS-DDR via AXI-MM interface. Then VCU IP reads data from PS-DDR, performs Video encoding/decoding and writes it back to the same memory. Lastly, in card to system direction, DMA reads PS-DDR via AXI-MM interface and writes to host system memory through PCIe.

Figure 1: VCU PCIe Hardware Block Diagram

Components, Features, and Functions

4-lane integrated PCIe block with a maximum link speed of 8 GT/s (GT/s is Giga transfers per second)

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Apart from PCIe related IPs, the design contains VCU IP.

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Software 

The below figure shows the PCIe software block diagram

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After booting the ZCU106 board with the SD images, to run the transcode use case first run the host side application mentioned as above and run the device application on the zcu106 device with the mentioned commands below. The host application will send file data to the device for transcoding it on the ZCU106 device and receives the transcoded data and saves it on to the host machine.

pcie_transcode

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