...
Code Block | ||
---|---|---|
| ||
CONFIG_FPGA=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_CMD_FPGA_LOADBP=y //Supports FPGA command. CONFIG_CMD_FPGA_LOADP=y //Supports loading a partial bitstream. CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y_LOADBP=y //Supports loading a partial bitstream from a bitstream buffer. CONFIG_CMD_FPGA_LOADFS=y //Supports loading a bitstream from a FAT filesystem. CONFIG_CMD_FPGA_LOADMK=y //Supports loading a bitstream from a image generated by mkimage. CONFIG_CMD_FPGA_LOAD_SECURE=y //Supports loading secure bitstream. |
For Zynq
Code Block | ||
---|---|---|
| ||
CONFIG_FPGA=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_CMD_FPGA_LOADBP=y //Supports FPGA command. CONFIG_CMD_FPGA_LOADFSLOADP=y //Supports loading a partial bitstream. CONFIG_CMD_FPGA_LOADMKLOADBP=y //Supports loading a partial bitstream from a bitstream buffer. CONFIG_CMD_FPGA_LOADPLOADFS=y //Supports loading a bitstream from a FAT filesystem. CONFIG_CMD_FPGA_XILINXLOADMK=y //Supports loading a bitstream from a image generated by mkimage. CONFIG_CMD_FPGA_ZYNQPLLOAD_SECURE=y //Supports loading secure bitstream. |
Device tree
Not required
Test Procedure
...
Code Block | ||
---|---|---|
| ||
ZynqMP> fpga info
Xilinx Device
Descriptor @ 0x000000007ffba260
Family: ZynqMP PL
Interface type: csu_dma configuration interface (ZynqMP)
Device Size: 1 bytes
Cookie: 0x0 (0)
Device name: zu9eg
Device Function Table @ 0x000000007ff975e8
PCAP status 0xa02
// Non secure bit-stream loading
tftpb 0x10000000 fpga.bin
fpga load 0 0x10000000 ${filesize}
//Secure bit-stream loading
//Encrypted bit-stream with device key
//arch = zynqmp; split = false; format = BIN the_ROM_image:
//{
//[aeskeyfile]bbram.nky
//[keysrc_encryption]bbram_red_key [encryption = aes, destination_device = pl] download.bit
//}
tftpb 0x10000000 fpga.bin
fpga loads 0 0x10000000 ${filesize} 2 0
//Authenticated bit-stream
//arch = zynqmp; split = false; format = BIN the_ROM_image:
//{
//[pskfile] psk0.pem
//[sskfile] ssk0.pem
//[auth_params] ppk_select = 0
//[fsbl_config]bh_auth_enable
//[authentication = rsa, destination_device = pl] download.bit
//}
tftpb 0x10000000 fpga.bin
fpga loads 0 0x10000000 ${filesize} 0 2
// Encrypted & Authenticated bit-steream
// To be done
|
Features
- Full Bitstream loading.
- Encrypted and Authenticated Full Bitstream loading.
- Readback of Bitstream(Configuration Data)
- PCAP status available through 'info' sub-command provides information about the state of bitstream programming.
- Bitstream loading is implemented as a blocking call to ensure completion of loading if the command returns without error.
- Relevant commit for ZynqUS+ (as of Xilinx release 2018.1): c055151
...