This article is intended to be a guide for helping you tweak tweaking the default PCW configuration to shape the traffic of the HP ports to help meet your system requirements.
Table of Contents
Table of Contents | ||
---|---|---|
|
Introduction
Performance through the HP ports is very dependent on the traffic patterns generated by the PL masters as well as non-deterministic traffic patterns driven by software running on the processors. Both sets of these masters will be competing for DDR access. The non-deterministic nature of software running on the processors makes it difficult to predict and achieve high DDR efficiency. However, you may be able to tweak the default configurations in the AFIFM, NIC, and DDRMC PS-PL interface, interconnect switches, DDR memory controller and APU QoS to help meet your system performance requirements.
This article does not address:
HPC, HPM, ACE, ACP , ACE or LPD ports
CCI or /QVN enablement
Impact of SMMU enablement
DDR QoS Controller
HP to DDR Data Path
Add snapshot of data path
AFIFM
The AFIFM controls the AXI interface per HP port that bridges the PS and PL.
RDCTRL/WRCTRL: Enable static or dynamic QoS
RDISSUE/WRISSUE: Read/write command issuing capability
RDQoS/WRQoS: Static QoS value
Info |
---|
These registers may be changed dynamically. |
NIC
...
Traffic Shaping
<Add some description here>
PS-PL Interface
The PS-PL interface is comprised of an AXI FIFO interface (AFI) per port to bridge the PS and PL domains. The main controls here are the QoS and the issuing capability per port. The QoS specifies the priority of the transaction which is also used to map the channel into traffic classes in the DDR memory controller. The QoS may be static or dynamic depending on your system needs. The issuing capability defines how many HP outstanding transactions may be in-flight at a given time.
Info |
---|
To maximize performance, the PL devices should be configured with an AXI bus width of 128 bits and an AXI burst length (BL) of 16. |
The PS-PL interface will convert AXI burst lengths greater than 16, however this conversion may negatively impact performance when heavily loaded.
Port | Base Address |
---|---|
HP0 | 0xFD380000 |
HP1 | 0xFD390000 |
HP2 | 0xFD3A0000 |
HP3 | 0xFD3B0000 |
Registers Per Port
Register | Offset | BIts | Description |
---|---|---|---|
RDCTRL | 0x0 | [2] | FABRIC_QOS_EN: 0-Enable static QoS, 1-Enable dynamic QoS (PL AXI sideband pass-through) |
RDISSUE | 0x4 | [3:0] | CAPABILITY: Read/write command issuing capability (0-15); Number of commands minus one |
RDQoS | 0x8 | [3:0] | VALUE: Static QoS value (0-15) |
WRCTRL | 0x14 | [2] | FABRIC_QOS_EN: 0-Enable static QoS, 1-Enable dynamic QoS (PL AXI sideband pass-through) |
WRISSUE | 0x18 | [3:0] | CAPABILITY: Read/write command issuing capability (0-15); Number of commands minus one |
WRQoS | 0x1c | [3:0] | VALUE: Static QoS value (0-15) |
Info |
---|
These registers are dynamic. |
FPD Interconnect Switches
The interconnect switches are comprised of the NIC-400 with QoS-400 ARM IP which provides two traffic regulation mechanisms.
Transaction rate regulation
Outstanding transaction regulation
Info |
---|
The FPD switches are clocked at the DDR reference clock, which defaults to 533 MHz. This equates to a theoretical data rate of 533 MHz * 128b / 8 = 8.528 GBps. |
FPD GPV base address: 0xFD700000
Registers
The FPD General Programmer's View (GPV) Module contains the QoS-400 registers for regulating the AXI traffic through the NIC-400 switches. The table below maps the “top” NIC-400 switches. The “bottom” NIC-400 switches also have their own resister set for regulating traffic as secondary level of control. Regulating the “bottom” switches is not investigated here.
Transaction Rate Regulation
When regulating the traffic with the QoS-400, you must specify one of these sets.
Peak rate, burstiness and average rate
Peak rate only
Burstiness and average rate
HP0 Registers | HP1 Registers | HP2 Registers | HP3 Registers | Description | ||||
---|---|---|---|---|---|---|---|---|
afifm2M_intfpd_aw_p | 0x47118 | afifm3M_intfpd_aw_p | 0x4A118 | afifm4M_intfpd_aw_p | 0x4B118 | afifm5M_intfpd_aw_p | 0x4C118 | AW channel peak rate |
afifm2M_intfpd_aw_b | 0x4711C | afifm3M_intfpd_aw_b | 0x4A11C | afifm4M_intfpd_aw_b | 0x4B11C | afifm5M_intfpd_aw_b | 0x4C11C | AW channel burstiness allowance |
afifm2M_intfpd_aw_rafifm2M | 0x47120 | afifm3M_intfpd_aw_rafifm2M | 0x4A120 | afifm4M_intfpd_aw_rafifm2M | 0x4B120 | afifm5M_intfpd_aw_r | 0x4C120 | AW channel average rate |
afifm2M_intfpd_ar_p | 0x47124 | afifm2Mafifm3M_intfpd_ar_pafifm2M | 0x4A124 | afifm4M_intfpd_ar_p | 0x4B124 | afifm2Mafifm5M_intfpd_ar_p | 0x4C124 | AR channel peak rate |
afifm2M_intfpd_ar_bafifm2M | 0x47128 | afifm3M_intfpd_ar_bafifm2M | 0x4A128 | afifm4M_intfpd_ar_bafifm2M | 0x4B128 | afifm5M_intfpd_ar_b | 0x4C128 | AR channel burstiness allowance |
afifm2M_intfpd_ar_rafifm2M | 0x4712C | afifm3M_intfpd_ar_r | 0x4A12C | afifm2Mafifm4M_intfpd_ar_r | 0x4B12C | afifm2Mafifm5M_intfpd_ar_r | 0x4C12C | AR channel average rate |
afifm2M_intfpd_qos_cntl | 0x4710C | afifm3M_intfpd_qos_cntl | 0x4A10C | afifm4M_intfpd_qos_cntl | 0x4B10C | afifm5M_intfpd_qos_cntl | 0x4C10C | Enable rate regulation |
Register | Field | Bits | Description |
---|---|---|---|
*_intfpd_aw_p | aw_p | [31:24] | Channel peak rate (8b fraction of transfers per cycle) |
*_intfpd_aw_b | aw_b | [15:0] | Channel burstiness (integer transfers) |
*_intfpd_aw_r | aw_r | [31:20] | Channel average rate (12b fraction of transfers per cycle) |
*_intfpd_ar_p | ar_p | [31:24] | Channel peak rate (8b fraction of transfers per cycle) |
*_intfpd_ar_b | ar_b | [15:0] | Channel burstiness (integer transfers) |
*_intfpd_ar_r | ar_r | [31:20] | Channel average rate (12b fraction of transfers per cycle) |
*_intfpd_qos_cntrl | en_awar_rate en_ar_rate en_aw_rate | [2] [1] [0] | Enable combined rate regulation Enable AR rate regulation Enable AW rate regulation |
Info |
---|
These registers are dynamic. |
Example
Regulate an HP port to an average rate of 10% of the interconnect data rate, but allow up to 4 catch-up transactions capped at 15% of the data rate.
BL = 16
MAX = 533 MTps
TPS_avg = 0.1 * 533M = 53.3 MTps
TPS_max = 0.15 * 533M = 79.95 MTps
Rate_avg = floor (256 / (100 * BL / %BW_avg)) = floor (4096 / (100 * 16 / 15)) = 38 (0x26)
Rate_peak = floor (4096 / (100 * BL / %BW_peak)) = floor (256 / (100 * 16 / 10)) = 1 (0x1)
Burstiness = 4
Outstanding transaction regulation
In the QoS-400 you may specify the maximum number of outstanding transactions allowed including fractional transactions for finer control. The actual number of transactions will modulate between the upper and lower value.
HP0 | HP1 | HP2 | HP3 | Description | ||||
---|---|---|---|---|---|---|---|---|
afifm2M_intfpd_max_ot | 0x47110 | afifm3M_intfpd_max_ot | 0x4A110 | afifm4M_intfpd_max_ot | 0x4B110 | afifm5M_intfpd_max_ot | 0x4C110 | Max number of outstanding transactions |
afifm2M_intfpd_max_comb_ot | 0x47114 | afifm3M_intfpd_max_ot | 0x4A114 | afifm4M_intfpd_max_ot | 0x4B114 | afifm5M_intfpd_max_ot | 0x4C114 | Max number of combined outstanding transactions |
afifm2M_intfpd_qos_cntl | 0x4710C | afifm3M_intfpd_qos_cntlafifm2M | 0x4A10C | afifm4M_intfpd_qos_cntlafifm2M | 0x4B10C | afifm5M_intfpd_qos_cntl | 0x4C10C | Enable outstanding transaction regulation |
Register | Field | Bits | Description |
---|---|---|---|
*_intfpd_max_ot | ar_max_oti ar_max_otf aw_max_oti aw_max_otf | [29:24] [23:16] [13:8] [7:0] | Integer part of max outstanding AR addresses (6b) Fraction part of max outstanding AR addresses (8b) Integer part of max outstanding AW addresses (6b) Fraction part of max outstanding AW addresses (8b) |
*_intfpd_max_comb_ot | awar_max_oti awar_max_otf | [14:8] [7:0] | Integer part of max combined outstanding AW/AR addresses (6b) Fraction part of max combined outstanding AW/AR addresses (8b) |
*_intfpd_qos_cntrl | en_awar_rate en_ar_rate en_aw_rate | [7] [6] [5] | Enable combined regulation of outstanding transactions Enable regulation of outstanding read transactions Enable regulation of outstanding write transactions |
Info |
---|
These registers may be changed dynamically. |
DDR QoS Controller
Disabled by default.
DDRC_URGENT: Enable read/write urgent sidebands per port. Same effect at aging counters.
...
are dynamic. |
Example
Regulate an HP port to 2.5 outstanding transactions.
oti = 2 (0x2)
otf = 256 * 0.5 = 128 (0x80)
DDR QoS Controller
The DDR QoS controller can throttle low latency and best effort traffic based on CAM levels to ensure video traffic does not get blocked. It also provides software the ability to trigger urgent AXI transactions on a per port basis to prevent higher priority traffic from blocking lower priority traffic.
DDR QoS Control Module base address: 0xFD090000
Urgent Transactions
Urgent transactions are enabled by default in FSBL which sets in the [rd/wr]_port_urgent_en bits in the PCFG[R/W]_n registers. Urgent transactions may be issued either through expiring aging counters in the DDRC or through software by writing to the DDRC_URGENT register in the DDR QoS Controller.
Register | Offset | Field | Bits | Description |
---|---|---|---|---|
DDRC_URGENT | 0x510 | ARURGENT_5 AWURGENT_5 ARURGENT_4 AWURGENT_4 ARURGENT_3 AWURGENT_3 | [13] [12] [11] [10] [9] [8] | Sideband signal to indicate a DDRC Port 5 read queue urgent transaction Sideband signal to indicate a DDRC Port 5 write queue urgent transaction Sideband signal to indicate a DDRC Port 4 read queue urgent transaction Sideband signal to indicate a DDRC Port 4 write queue urgent transaction Sideband signal to indicate a DDRC Port 3 read queue urgent transaction Sideband signal to indicate a DDRC Port 3 write queue urgent transaction |
Info |
---|
These registers are dynamic. |
QoS Throttle Control
The QoS DDR controller is designed to ensure that there is always space available in the CAMs for video traffic. By monitoring the individual CAM levels, the QoS DDR controller can throttle low latency and best effort traffic in favor of video traffic. The DBGCAM register can be used to monitor CAM levels to see if any are saturating.
Info |
---|
QoS throttle control is disabled by default |
Register | Offset | Field | Bits | Description |
---|---|---|---|---|
PORT_TYPE | 0x0 | PORT5_TYPE PORT4_TYPE PORT3_TYPE | [15:14] [13:12] [11:10] | Port 5 Type: 0x0-BE, 0x1-LL, 0x2-Video Port 4 Type: 0x0-BE, 0x1-LL, 0x2-Video Port 4 Type: 0x0-BE, 0x1-LL, 0x2-Video |
QOS_CTRL | 0x4 | PORT5_WR_CTRL PORT5_HPR_CTRL PORT5_LPR_CTRL PORT4_WR_CTRL PORT4_HPR_CTRL PORT4_LPR_CTRL PORT3_WR_CTRL PORT3_HPR_CTRL PORT3_LPR_CTRL | [21] [20] [19] [18] [17] [16] [15] [14] [13] | QoS throttle Control on Write channel QoS throttle Control on Read HPR channel QoS throttle Control on Read LPR channel QoS throttle Control on Write channel QoS throttle Control on Read HPR channel QoS throttle Control on Read LPR channel QoS throttle Control on Write channel QoS throttle Control on Read HPR channel QoS throttle Control on Read LPR channel |
RD_HPR_THRSLD | 0x8 | VALUE | [6:0] | Read HPR CAM Threshold Level |
RD_LPR_THRSLD | 0xC | VALUE | [6:0] | Read LPR CAM Threshold Level |
WR_THRSLD | 0x10 | VALUE | [6:0] | Write CAM Threshold Level |
Info |
---|
These registers are dynamic. |
DDR Memory Controller
The DDR memory controller is based on the uMCTL2 DDR Memory Controller IP from Synopsys. The four HP ports funnel down to three ports S3-S5 on the DDR memory controller through the interconnect switch network. Since this is a multi-port memory controller, arbitration occurs based on the priority and direction of each request in an effort to optimize the DDR accesses.
DDRC Module base address: 0xFD070000
Arbitration
The Port Arbiter (PA) is responsible for arbitrating between the AXI Port Interfaces (XPI) and forwarding the commands to the DDR Controller (DDRC. Each of these ports on the DDRC are ) for scheduling.
Read/write arbitration
Reads
Stay on reads as long as there is a timed-out read port or an expired VPR with available credit
Switch to writes if there is a timed-out write port or expired-VPW with available credit
Switch to writes when there is no read credit left and there is a pending write with available credit
Reads are prioritized over writes when everything else is equal
Writes
Stay on the writes as long as there is a timed-out write port or expired-VPW with available credit
Switch to reads if there is a timed-out read port or expired-VPR with available credit
Switch to reads if there is an HPR read port with available credit
Switch to reads when there is no write credit left and there is a pending read with available credit
2-priority level arbitration based on port aging and expired-VPR/VPW commands
2-priority level arbitration for read requests based on DDRC read priorities (HPR/LPR-VPR)
16-priority level arbitration based external AXI QoS inputs
Round-robin arbitration when everything else is equal
Each XPI supports a single read address queue (RAQ) and a single write address queue (WAQ), so it’s recommended to restrict each port to a single traffic class to prevent head-of-line blocking (HOLB).
Port Control
The Port Control registers allow software to enable and disable the DDRC ports. This can be helpful for debugging or dynamically managing ports with software.
Register | Offset | Field | Bits | Description |
---|---|---|---|---|
PCTRL_0 | 0x490 | port_en | [0] | Enables port 0 |
PCTRL_1 | 0x540 | port_en | [0] | Enables port 1 |
PCTRL_2 | 0x5F0 | port_en | [0] | Enables port 2 |
PCTRL_3 | 0x6A0 | port_en | [0] | Enables port 3 |
PCTRL_4 | 0x750 | port_en | [0] | Enables port 4 |
PCTRL_5 | 0x800 | port_en | [0] | Enables port 5 |
Info |
---|
These registers are dynamic. |
Traffic Classes
The DDRC maps the QoS values on each port are mapped into traffic classes. Video class traffic (VPR/VPW) has a timer associated with each command. When the timer reaches zero, the command is considered expired and gets elevated to the highest priority whether the command is in an XPI or a CAM.
Traffic Class | Read QoS Value (default) | Read Priority Mapping | Write QoS Value (default) | Write Priority Mapping |
---|---|---|---|---|
Best Effort | 0-3 | LPR | 0-7 | NPW |
Video | 4-11 | VPR | 8-15 | VPW |
Low Latency | 12-15 | HPR | N/A | N/A |
The traffic class mappings are register configurable,
...
however you should not need to modify these. Please see ZU+ Register Reference for details if you need to modify these mappings.
Register
PCFGQOS0_n/PCFGQOS1_n: Port 'n' Read QoS Configuration RegistersRegister 0
PCFGWQOS0_n/PCFGWQOS1_n: Port 'n' Write QoS Configuration Registers
...
Read QoS Value
...
Traffic Class
...
0-3
...
Best Effort
...
4-11
...
Video
...
12-15
...
Low Latency
...
Write QoS Value
...
Traffic
...
0-7
...
Best Effort
...
8-15
...
Video
Info |
---|
Quasi dynamic registers group 3 |
VPR/VPW timeouts
Variable priority timeouts can be modified based on latency requirements.
PCFGQOS1_n
PCFGWQOS1_nRegister 0
Info |
---|
These registers are quasi dynamic group 3 and can only be modified when the DDRC is empty. |
These registers are not configurable in the PCW. If you need to remap the traffic classes, you must patch the psu_init.c.
Variable Priority Timeouts
Variable priority timeouts can be modified to trade-off latency for throughput.
Register | Offset | Field | Bits | Description |
---|---|---|---|---|
PCFGQOS1_3 | 0x6A8 | rqos_map_timeout | [10:0] | Timeout value for read transactions on port 3 |
PCFGWQOS1_3 | 0x6B0 | wqos_map_timeout | [10:0] | Timeout value for write transactions on port 3 |
PCFGQOS1_4 | 0x758 | rqos_map_timeout | [10:0] | Timeout value for read transactions on port 4 |
PCFGWQOS1_4 | 0x6B0 | wqos_map_timeout | [10:0] | Timeout value for write transactions on port 4 |
PCFGQOS1_5 | 0x808 | rqos_map_timeout | [10:0] | Timeout value for read transactions on port 5 |
PCFGWQOS1_5 | 0x810 | wqos_map_timeout | [10:0] | Timeout value for write transactions on port 5 |
Info |
---|
These registers are static and must be set while the DDRC is reset. |
These registers are not configurable in the PCW, however psu_init configures with a default value. If you want to modify the timeout values, you must patch the psu_init.c.
Port Aging
Port aging provides a mechanism to elevate an XPI port's priority when it has a request, but has not been serviced. When the aging timer counts down to zero, the port is elevated to the highest priority equivalent to an expired variable priority command.
Port aging is disabled by default
Registers | Offset | Field | Bits | Description |
---|---|---|---|---|
PCFGR_3 | 0x614 | rd_port_aging_en rd_port_priority | [12] [9:0] | Enable aging function on read port 3 Initial load value of read aging counters |
PCFGW_3 | 0x618 | wr_port_aging_en wr_port_priority | [12] [9:0] | Enable aging function on write port 3 Initial load value of read aging counters |
PCFGR_4 | 0x6C4 | rd_port_aging_en rd_port_priority | [12] [9:0] | Enable aging function on read port 4 Initial load value of read aging counters |
PCFGW_4 | 0x6C8 | wr_port_aging_en wr_port_priority | [12] [9:0] | Enable aging function on write port 4 Initial load value of read aging counters |
PCFGR_5 | 0x774 | rd_port_aging_en rd_port_priority | [12] [9:0] | Enable aging function on read port 5 Initial load value of read aging counters |
PCFGW_5 | 0x778 | wr_port_aging_en wr_port_priority | [12] [9:0] | Enable aging function on write port 5 Initial load value of read aging counters |
Info |
---|
These registers are static and must be set while the DDRC is reset. |
Address mapping
Remap the Bank Groups, Banks, Column and Row address lines.
...
ADDRMAP0
...
ADDRMAP0
...
ADDRMAP0
...
ADDRMAP0
...
These registers are not configurable in the PCW. If you want to implement port aging, you must patch the psu_init.c.
Address Mapper
The address mapper allow you to map the rank, bank group (DDR4-only), bank, column and row address lines to optimize your memory accesses based on your traffic patterns. The twelve ADDRMAP registers map individual address lines to the HIF address which is the address generated by the XPI.
The HIF address is a word address. The DDR address is a byte address.
The ZCU102 has 4 GB DDR4 x64 DIMM with a burst length of 8. The table below shows the default address mapping generated by Vivado.
By default BG0 is mapped to A6 so consecutive bursts will ping-pong between bank groups to reduces access latency. (This may not be true for earlier Vivado versions)
DDR4_64 | A31 | A30 | A29 | A28 | A27 | A26 | A25 | A24 | A23 | A22 | A21 | A20 | A19 | A18 | A17 | A16 | A15 | A14 | A13 | A12 | A11 | A10 | A9 | A8 | A7 | A6 | A5 | A4 | A3 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HIF | A28 | A27 | A26 | A25 | A24 | A23 | A22 | A21 | A20 | A19 | A18 | A17 | A16 | A15 | A14 | A13 | A12 | A11 | A10 | A9 | A8 | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
PHY | R14 | R13 | R12 | R11 | R10 | R9 | R8 | R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0 | B1 | B0 | BG1 | C9 | C8 | C7 | C6 | C5 | C4 | C3 | BG0 | C2 | C1 | C0 |
Register | Address Mapping |
---|---|
ADDRMAP0 | Rank |
ADDRMAP1 | Bank |
ADDRMAP{2:4} | Column |
ADDRMAP{5:7} | Row |
ADDRMAP8 | Bank Group |
ADDRMAP{9:11} | Row |
Info |
---|
These registers are static and must be set while the DDRC is reset |
...
. |
These registers are not fully configurable in the PCW. If you want to remap the address lines, you must patch the psu_init.c.
Content Addressable Memory (CAM)
The read CAM has 64 command entries and which is split between the LPR and VPR classes.
...
SCHED
...
into HPR and LPR/VPR sections. This ratio can be changed in the SCHED register if either of these queues are getting saturated. The write CAM is fixed at 64 command entries.
Register | Offset | Field | Bits | Description |
---|---|---|---|---|
SCHED | 0x250 | lpr_num_entries | [13:8] | Number of entries in the low priority transaction store minus one. Number of entries in high priority transaction store = 64 - (lpr_num_entries + 1) |
Info |
---|
These registers are static and must be set while the DDRC is reset. |
These registers are not configurable in the PCW. If you want to reallocate the HPR and LPR transaction stores in the read CAM, you must patch the psu_init.c.
Debug/Status Registers
These registers are for debugging and polling the status of the DDRC ports. DBGCAM monitors the CAM levels, while PSTAT monitors the XPI outstanding commands.
Register | Offset | Field | Bits | Description |
---|---|---|---|---|
DBGCAM | 0x308 | dbg_w_q_depth dbg_lpr_q_depth dbg_hpr_q_depth | [22:16] [14:8] [6:0] | Write queue depth Low priority read queue depth High priority read queue depth |
PSTAT | 0x3FC | wr_port_busy_5 wr_port_busy_4 wr_port_busy_3 wr_port_busy_2 wr_port_busy_1 wr_port_busy_0 rd_port_busy_5 rd_port_busy_4 rd_port_busy_3 rd_port_busy_2 rd_port_busy_1 rd_port_busy_0 | [21] [20] [19] [18] [17] [16] [5] [4] [3] [2] [1] [0] | Indicates if there are outstanding writes for port 5 Indicates if there are outstanding writes for port 4 Indicates if there are outstanding writes for port 3 Indicates if there are outstanding writes for port 2 Indicates if there are outstanding writes for port 1 Indicates if there are outstanding writes for port 0 Indicates if there are outstanding reads for port 5 Indicates if there are outstanding reads for port 4 Indicates if there are outstanding reads for port 3 Indicates if there are outstanding reads for port 2 Indicates if there are outstanding reads for port 1 Indicates if there are outstanding reads for port 0 |
Info |
---|
These registers are read-only |
Writing Quasi Dynamic Group 3 Registers
Info |
---|
Please see the ZU+ TRM UG1085 (1), Ch. 17 DDR Memory Controller, Group 3: Registers that can be written when controller is empty |
APU
You may need to adjust the APU QoS if the HP ports are significantly impacting the DDR accesses. The result may be software that freezes or runs very slowly.
Info |
---|
The APU read and write QoS priority is set to lowest priority (0) by FSBL |
APU Module base address: 0xFD5C0000
Registers
Register | Offset | Fields | BIts | Description |
---|---|---|---|---|
ACE_CTRL | 0x60 | AWQOS ARQOS | [19:16] [3:0] | ACE outgoing AWQOS value (0-15) ACE outgoing ARQOS value (0-15) |
Info |
---|
These registers are dynamic. |
Test Bench
Vitis 2020.1
Petalinux 2020.1
ZCU102
Traffic Generators
The IPI block design for the test bench has a traffic generator (TG) connected to each HP port. Each TG is configured with a 128b 128-bit data bus at 200MHz and operates as a greedy master flooding the NIC FPD interconnect and DDRMC DDR with equal read and write traffic. The theoretical data rate of each TG is 3.2 GBps per channel. The only default flow control is the back pressure from the AXI bus.
...
Monitor Software
...
Throughput is measured at each DDRMC port using the hard APMs. Monitor software running on the RPU prints echos the data measured from the APMseach hard APM to a terminal. Running the monitor on the RPU from OCM allows us to see how DDR throughput and efficiency is affected take snapshots of the DDR traffic when running a high level OS like Linux on the APU with heavy HP traffic conditions.
Traffic Shaping
...
. Since there is no dependency on the DDR memory, the monitor software will not get blocked from accessing its memory. An advantage of this approach is it does not require JTAG to read the APM registers.
Traffic Shaping on ZCU102
Start off with 4 greedy masters and try to shape the traffic to meet an arbitrary requirement.
Calculate max DDR bandwidth of 17 GBps and efficiency with defaults.
AFI
Latency sensitive masters (APU) (Highest default priority, 14)
Real-time master (HP0:HDMI) (Video Priority, 11)
Isochronous (HP1:Video) (Video Priority, 8)
Greedy master (HP2:HDD) (BE, 3)
Greedy master (HP3:DMA) (BE 0)
QoS-400
Limit video ports
Limit greedy master
Urgent
Set one of greedy masters as urgent in software
Suggest setting port aging
Address Mapper
Maybe show different buffer boundaries vs performance
Related Links
Zynq UltraScale+ Device Technical Reference Manual (UG1085)
ARM® CoreLink™ NIC-400 Network Interconnect
ARM® CoreLink™ QoS-400 Network Interconnect Advanced Quality of Service
Quality of Service (QoS) in ARM Systems: An Overview, Ashley Stevens, July 2014
Child Pages
Child pages (Children Display) |
---|
...