This article is intended to be a guide for tuning the default configuration to shape the traffic of the HP ports to help meet your system throughput requirements.

1 Introduction
2 PS-PL Interface
- 2.1 Registers
3 FPD Interconnect Switches
- 3.1 Registers
- 3.2 Transaction Rate Regulation
- 3.3 Outstanding transaction regulation
4 DDR QoS Controller
- 4.1 QoS Throttle Control
- 4.2 Urgent Transactions
5 DDR Memory Controller
- 5.1 Port Control
- 5.2 Traffic Classes
- 5.3 Variable Priority Timeouts
- 5.4 Port Aging
- 5.5 PA Arbitration
- 5.6 Content Addressable Memory (CAM)
- 5.7 Address Mapper
- 5.8 Debug/Status Registers
- 5.9 Writing Quasi Dynamic Group 3 Registers
6 APU
- 6.1 Registers
7 Test Bench
- 7.1 Firmware
- 7.2 Software
8 Related Links

Introduction

Performance through the HP ports is very dependent on the traffic patterns generated by the PL masters as well as non-deterministic traffic patterns driven by software running on the processors. Both sets of masters will be competing for DDR access. The non-deterministic nature of software running on the processors makes it difficult to accurately model for optimal DDR efficiency. However, you may be able to iteratively tune the default configurations to help meet your system performance requirements. This is not an exhaustive list of the available controls, but the most effective knobs to help shape the HP traffic. The data path from the HP ports in the PL to the DDR memory controller is shown below.

Xilinx Wiki

Traffic Shaping of HP Ports on Zynq UltraScale+

Table of Contents

Introduction