Versions Compared

Old Version 18

changes.mady.by.user Sam Hendrix

Saved on

compared with

New Version 19

changes.mady.by.user William Cassells

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Table 1: Supported PL DRAM Configurations

Configuration

DDR3/3L

DDR4

Component, 1 rank

x4, x8, x16

x4, x8, x16

Component, 2 rank

x4, x8, x16

x4, x8, x16

1 slot, 1 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM, LRDIMM

1 slot, 2 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM, LRDIMM

1 slot, 4 rank

RDIMM

LRDIMM

2 slot, 1 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM, LRDIMM

2 slot, 2 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM, LRDIMM

2 slot, 4 rank

LRDIMM (UltraScale+ Only)

Configuration

LPDDR3

1 rank, Component DRAM

x16, x32

 Table 2: Supported PS DRAM Configurations

Configuration

DDR3/3L

DDR4

Component, 1 rank

x8, x16

x8, x16

Component, 2 rank

x8, x16

x8, x16

1 slot, 1 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM

1 slot, 2 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM

1 slot, 4 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM

2 slot, 1 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM

2 slot, 2 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM

2 slot, 4 rank

RDIMM, UDIMM, SODIMM

RDIMM, UDIMM, SODIMM

Configuration

LPDDR3

LPDDR4

Component, 1 rank

x32 or x64, ECC Option

x16 or x32, ECC Option

Component, 2 rank

x32 or x64, ECC Option

x16 or x32, ECC Option

PL DRAM IP Drive Strength, ODT, and VREF Configuration

...

Table 3: PL DDR4 FPGA drive strength & ODT configurations

UltraScale PL DDR4

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

40

1 slot, 1 rank

40

40

2 slot, 1 rank

40

40

1 slot, 2 rank

40

40

2 slot, 2 rank

40

60

1 slot, 4 rank

40

40

 Table 4: PL DDR4 DRAM drive strength and ODT configurations

UltraScale PL DDR4

DRAM Strength, Ohm

RTT(nom), Ohm

RTT(park), Ohm

Component, 1 or 2 rank

34

40

N/A

1 slot, 1 rank

34

40

N/A

2 slot, 1 rank

34

60

40

1 slot, 2 rank

34

120

60

2 slot, 2 rank

34

240

60

1 slot, 4 rank

34

40

60

 Table 5: PL DDR4 VREF configurations

UltraScale PL DDR4 (Vcc = 1.2V)

WRITE VREF, V

READ VREF, V

WRITE VREF, %

READ VREF, %

Component, 1 or 2 rank

0.88

0.88

73%

73%

1 slot, 1 rank

0.93

0.93

78%

78%

2 slot, 1 rank

0.97

1.01

81%

84%

1 slot, 2 rank

0.93

0.97

78%

81%

2 slot, 2 rank

1.00

0.99

83%

83%

1 slot, 4 rank

0.93

0.97

78%

81%

UltraScale PL DDR3

  • Table 6 provides PL DDR3 FPGA drive strength & ODT configuration

    • FPGA Slew Rate is always FAST

  • Table 7 provides PL DDR3 DRAM drive strength and ODT configuration

Table 6: PL DDR3 FPGA drive strength & ODT configuration

UltraScale PL DDR3

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

40

1 slot, 1 rank

40

40

2 slot, 1 rank

40

40

1 slot, 2 rank

40

40

2 slot, 2 rank

40

60

1 slot, 4 rank

40

40

 Table 7: PL DDR3 DRAM drive strength and ODT configuration

UltraScale PL DDR3

DRAM Strength, Ohm

RTT(nom), Ohm

RTT(wr), Ohm

Component, 1 or 2 rank

40

40

Disabled

1 slot, 1 rank

40

40

Disabled

2 slot, 1 rank

40

40

60

1 slot, 2 rank

40

120

60

2 slot, 2 rank

40

60

120

1 slot, 4 rank

40

120

60

 

UltraScale+ PL DDR4

  • Table 8 provides PL DDR4 FPGA drive strength & ODT configurations

    • FPGA Slew Rate is always FAST

  • Table 9 provides PL DDR4 DRAM drive strength and ODT configurations

  • Table 10 provides PL DDR4 VREF configurations

Table 8: PL DDR4 FPGA drive strength & ODT configurations

UltraScale+ PL DDR4

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

40

1 slot, 1 rank

40

60

2 slot, 1 rank

40

60

1 slot, 2 rank

40

60

2 slot, 2 rank

40

60

1 slot, 4 rank

40

60

2 slot, 4 rank

40

60

 

Table 9: PL DDR4 DRAM drive strength and ODT configurations

UltraScale+ PL DDR4

DRAM Strength, Ohm

RTT(nom), Ohm

RTT(park), Ohm

Component, 1 or 2 rank

34

40

N/A

1 slot, 1 rank

34

40

N/A

2 slot, 1 rank

34

60

40

1 slot, 2 rank

34

120

60

2 slot, 2 rank

34

240

60

1 slot, 4 rank

34

40

60

2 slot, 4 rank

34

40

60

 

Table 10: PL DDR4 VREF configurations

UltraScale+ PL DDR4 (Vcc = 1.2V)

WRITE VREF, V

READ VREF, V

WRITE VREF, %

READ VREF, %

Component, 1 or 2 rank

0.88

0.88

73%

74%

1 slot, 1 rank

0.93

0.87

78%

73%

2 slot, 1 rank

0.97

0.98

81%

82%

1 slot, 2 rank

0.93

0.92

78%

77%

2 slot, 2 rank

1.00

0.99

83%

83%

1 slot, 4 rank

0.93

0.89

78%

74%

2 slot, 4 rank

0.93

0.95

78%

79%

 

UltraScale+ PL DDR3

  • Table 11 provides PL DDR3 FPGA drive strength & ODT configurations

    • FPGA Slew Rate is always FAST

  • Table 12 provides PL DDR3 DRAM drive strength and ODT configurations

Table 11: PL DDR3 FPGA drive strength & ODT configurations

UltraScale+ PL DDR3

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

40

1 slot, 1 rank

40

40

2 slot, 1 rank

40

40

1 slot, 2 rank

40

40

2 slot, 2 rank

40

60

1 slot, 4 rank

40

40

Table 12: PL DDR3 DRAM drive strength and ODT configurations

UltraScale+ PL DDR3

DRAM Strength, Ohm

RTT(nom), Ohm

RTT(wr), Ohm

Component, 1 or 2 rank

40

40

Disabled

1 slot, 1 rank

40

40

Disabled

2 slot, 1 rank

40

40

60

1 slot, 2 rank

40

120

60

2 slot, 2 rank

40

60

120

1 slot, 4 rank

40

120

60

Manually finding the DRAM Configuration Settings

...

Table 13: PS DDR4 FPGA drive strength & ODT configurations

UltraScale+ PS DDR4

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

34

40

1 slot, 1 rank

34

40

1 slot, 2 rank

34

40

Table 14: PS DDR4 DRAM drive strength and ODT configurations

UltraScale+ PS DDR4

DRAM Strength, Ohm

RTT(nom), Ohm

RTT(park), Ohm

Component, 1 rank

34

40

40

Component, 2 rank

34

48

240

1 slot, 1 rank

34

40

40

1 slot, 2 rank

34

48

240

Table 15: PS DDR4 VREF (initial value) configurations

UltraScale+ PS DDR4

DC Calculation (Vcc = 1.2V)

WRITE VREF, V

WRITE VREF, %

All configurations

0.92

76%

 

Zynq MPSoC PS LPDDR4

  • Table 16 provides PS LPDDR4 FPGA drive strength & ODT configurations

    • FPGA Slew Rate can’t be adjusted and is always FAST

  • Table 17 provides PS LPDDR4 DRAM drive strength and ODT configurations

  • Table 18 provides PS LPDDR4 VREF (initial value) configurations

Table 16: PS LPDDR4 FPGA drive strength & ODT configurations

UltraScale+ PS LPDDR4

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

40

Component, 1 or 2 rank ECC

40

40

 

Table 17: PS LPDDR4 DRAM drive strength and ODT configurations

UltraScale+ PS LPDDR4

DRAM Driver Strength, Ohm

CA RTT, Ohm

DQ RTT, Ohm

Component, 1 or 2 rank

40

48

40

Component, 1 or 2 rank ECC

40

48

40

 

Table 18: PS LPDDR4 VREF (initial value) configurations

UltraScale+ PS LPDDR4

DC Calculation (Vcc = 1.1V)

WRITE VREF CA, V

WRITE VREF DQ, V

WRITE VREF CA, %

WRITE VREF DQ, %

Component, 1 or 2 rank

0.34

0.45

31%

41%

Component, 1 or 2 rank ECC

0.34

0.44

31%

40%

 

Zynq MPSoC PS DDR3/3L

  • Table 19 provides PS DDR3 FPGA drive strength & ODT configurations

    • FPGA Slew Rate can’t be adjusted and is always FAST

  • Table 20 provides PS DDR3 DRAM drive strength and ODT configurations

...

Table 19: PS DDR3 FPGA drive strength & ODT configurations

UltraScale+ PS DDR3/3L

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

40

1 slot, 1 rank

40

40

1 slot, 2 rank

40

40

1 slot, RDIMM, 1 rank

40

40

1 slot, RDIMM, 2 rank

40

60

 

Table 20: PS DDR3 DRAM drive strength and ODT configurations

UltraScale+ PS DDR3/3L

DRAM Strength, Ohm

RTT(nom), Ohm

RTT(wr), Ohm

Component, 1 rank

40

60

Disabled

Component, 2 rank

40

120

60

1 slot, 1 rank

40

60

Disabled

1 slot, 2 rank

40

120

60

1 slot, RDIMM, 1 rank

40

60

Disabled

1 slot, RDIMM, 2 rank

40

120

60

 

UltraScale+ PS LPDDR3

  • Table 21 provides PS LPDDR3 FPGA drive strength & ODT configurations

    • FPGA Slew Rate can’t be adjusted and is always FAST

  • Table 22 provides PS LPDDR3 DRAM drive strength and ODT configurations

...

Table 21: PS LPDDR3 FPGA drive strength & ODT configurations

UltraScale+ PS LPDDR3

FPGA Driver Strength, Ohm

FPGA ODT, Ohm

Component, 1 or 2 rank

40

120

 

Table 22: PS LPDDR3 DRAM drive strength and ODT configurations

UltraScale+ PS LPDDR3

DRAM Driver Strength, Ohm

RTT(nom), Ohm

Component, 1 or 2 rank

34.3

120

 

Manually finding the DRAM Configuration Settings

...

Table 23: PL IBIS Decoder

Xilinx PL IBIS Model Settings

Base Model

BANK-TYPE_IOSTANDARD_SLEW_OUTPUT-IMPEDANCE*_INPUT-ODT_PRE-EMPHASIS

  • OUTPUT-IMPEDANCE or OUTPUT-DRIVE-STRENGTH depending on IOSTANDARD

Model Setting

Options

Available Documentation

BANK-TYPE

HP, HR, HD

UG571, Ch  1, I/O Tile Overview

IOSTANDARD

See supported I/O standard for BANK-TYPE

HP & HR: UG571, Ch 1, Supported I/O Standards and Terminations
HD: UG571, Ch 3, HD I/O Supported Standards

SLEW

FAST, MEDIUM, SLOW

UG571, Ch 1, Output Slew Rate Attributes

OUTPUT-IMPEDANCE (Ohm)*

40, 48, 60 or None

UG571, Ch 1, Source Termination Attribute (OUTPUT_IMPEDANCE)

OUTPUT-STRENGTH (mA)*

4, 8, 12 or 16

UG571, Ch 1, Output Drive Strength Attributes

INPUT-ODT (Ohm)

40, 48, 60, 120, 240 or None

UG571, Ch 1, On-Die Termination (ODT) Attribute

PRE-EMPHASIS

PE1600 or PE2400

UG571, Ch 1, Transmitter Pre-Emphasis

 

All models (except for LVDS*) will contain Bank Type, IOStandard, Slew Rate and Output Impedance/Drive Strength.

...

Table 24: PL DDR4 IBIS Models

Example DDR4 IBIS Models

Signal Name

Model Name

Model Settings

DQ, DQS, DM

HP_POD12_DCI_F_OUT40_IN40_PE2400

Bank type: HP
IO Standard: POD
Bank Voltage: 1.2V
Digitally Controlled Impedance (DCI)
Slew rate: Fast
Output Impedance: 40 ohm
Input ODT: 40 Ohm
Pre-Emphasis enabled

Clock, Address & Command

HP_SSTL12_DCI_F_OUT40

Bank type: HP
IO Standard: SSTL
Bank Voltage: 1.2V
DCI
Slew rate: Fast
Output Impedance: 40 ohm

Xilinx Zynq PS DDR IBIS Decoder

...

Table 25: Zynq PS DDR IBIS Decoder

Zynq PS DDR IBIS Decoder

Base Model

 DWC_D5MXY_Z_MS

X

IO Type

C

Clock, Command, Control, Address

P

Data, Data Mask

Q

Data Strobe

Y

Memory Technology

3

DDR3

3L

DDR3L

L3

LPDDR3

4

DDR4

L4

LPDDR4

Z*

Output Impedance and/or Input Termiantion

  • Output and termination impedances are not adjustable on the PS DDR controller.

xx

Ouput impedance
xx = 34 ohms (DDR4)
xx = 40 ohms (DDR3, DDR3L, LPDDR3, LPDDR4)

ODTxx

input termination
xx = 40 ohms (DDR3, DDR3L)

xxODTyy

Output Impedance with input termination
(DDR4, LPDDR3 & LPDDR4)
xx = 34 ohms (DDR4)
xx = 40 ohms (LPDDR3)
xx = 80 ohms (LPDDR4)
yy = 40 ohms (DDR4, LPDDR4)
yy = 120 ohms (LPDDR3)

MS

Model Selector

 

The DQ and DQS models support the Model Selector feature.  This is indicated by the "_MS" suffix. 
This will point the simulator to the [Model Selector] keyword in the IBIS file.
The [Model Selector] keyword defines the ODT behavior.

Zynq PS DDR IBIS Examples

Table 26: PS DDR4

DDR4

Signal Name

Model Name

Notes

PS_DDR4_CK_P/N (OUT)

DWC_D5MC4_34

 Clock

PS_DDR4_A* (OUT)

DWC_D5MC4_34

Applies to Address, Command and Control

PS_DDR4_DQ* (IN/OUT)

DWC_D5MP4_34ODT_MS

See Model Selector Example

PS_DDR4_DQS* (IN/OUT)

DWC_D5MQ4_34ODT_MS

See Model Selector Example

Model Selector Example

DWC_D5MP4_34ODT_MS

DWC_D5MP4_34 or DWC_D5MP4_34ODT40

DWC_D5MQ4_34ODT_MS

DWC_D5MP4_34 or DWC_D5MP4_34ODT40

Table 27: PS LPDDR4

LPDDR4

Signal Name

Model Name

Notes

PS_LPDDR4_CK_P/N (OUT)

DWC_D5MCL4_40

 Clock

PS_LPDDR4_A* (OUT)

DWC_D5MCL4_40

Applies to Address, Command and Control

PS_LPDDR4_DQ* (IN/OUT)

DWC_D5MPL4_80ODT_MS

See Model Selector Example

PS_LPDDR4_DQS* (IN/OUT)

DWC_D5MQL4_80ODT_MS

See Model Selector Example

Model Selector Example

DWC_D5MPL4_80ODT_MS

DWC_D5MPL4_40 or DWC_D5MPL4_80ODT40

DWC_D5MQL4_80ODT_MS

DWC_D5MQL4_40 or DWC_D5MQL4_80ODT40

 

Table 28: PS DDR3

DDR3

Signal Name

Model Name

Notes

PS_DDR3_CK_P/N (OUT)

DWC_D5MC3_40

 Clock

PS_DDR3_A* (OUT)

DWC_D5MC3_40

Applies to Address, Command and Control

PS_DDR3_DQ* (IN/OUT)

DWC_D5MP3_ODT_MS

See Model Selector Example

PS_DDR3_DQS* (IN/OUT)

DWC_D5MQ3_ODT_MS

See Model Selector Example

Model Selector Example

DWC_D5MP3_ODT_MS

DWC_D5MP3_40 or DWC_D5MP3_ODT40

DWC_D5MQ3_ODT_MS

DWC_D5MQ3_40 or DWC_D5MQ3_ODT40

 

Table 29: PS DDR3L

DDR3L

Signal Name

Model Name

Notes

PS_DDR3L_CK_P/N (OUT)

DWC_D5MC3L_40

 Clock

PS_DDR3L_A* (OUT)

DWC_D5MC3L_40

Applies to Address, Command and Control

PS_DDR3L_DQ* (IN/OUT)

DWC_D5MP3L_ODT_MS

See Model Selector Example

PS_DDR3L_DQS* (IN/OUT)

DWC_D5MQ3L_ODT_MS

See Model Selector Example

Model Selector Example

DWC_D5MP3L_ODT_MS

DWC_D5MP3L_40 or DWC_D5MP3L_ODT40

DWC_D5MQ3L_ODT_MS

DWC_D5MQ3L_40 or DWC_D5MQ3L_ODT40

 

Table 30: PS LPDDR3

LPDDR3

Signal Name

Model Name

Notes

PS_LPDDR3_CK_P/N (OUT)

DWC_D5MCL3_40

 Clock

PS_LPDDR3_A* (OUT)

DWC_D5MCL3_40

Applies to Address, Command and Control

PS_LPDDR3_DQ* (IN/OUT)

DWC_D5MPL3_40ODT_MS

See Model Selector Example

PS_LPDDR3_DQS* (IN/OUT)

DWC_D5MQL3_40ODT_MS

See Model Selector Example

Model Selector Example

DWC_D5MPL3_40ODT_MS

DWC_D5MPL3_40 or DWC_D5MPL3_40ODT120

DWC_D5MQL3_40ODT_MS

DWC_D5MQL3_40 or DWC_D5MQL3_40ODT120  

Available Resources for HyperLynx and ADS Simulation Tools

...

Figure 39: IBIS File Modification for Probe Point

 

This section has highlighted some of the settings for HyperLynx DDRx.  For a complete guide on using HyperLynx DDRx, please see AR# 70873.