Multi-Rate GTY

This example describes a Versal GTY multi-rate design using the following configuration:

• Two rates: 10G and 25G switchable line rates

• Single GTY lane connected through SFP on VCK190/VMK180 evaluation board

VCK190/VMK180

https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Multi-Rate%20GTY

2020.2

Simplex TX/RX

This blog post shows how to combine Simplex TX/RX cores for several quads in IP Integrator

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-GTY-how-to-combine-Simplex-TX-RX-cores-for-several-quads/ba-p/1178478

2020.2

GTY Simulation

This blog entry covers a GTY simulation example, demonstrating how the GTY comes out of reset, and performs rate change.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-GTY-Simulation-Initialization-Reset-and-Rate-Change/ba-p/1176867

2020.2

Combine Within GT Quad

This example introduces the design flow on combining different IP within one quad with the Xilinx Vivado Integrated Design Environment.

VCK190

https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Combine_within_GT_quad

2020.2

GTY and GTY/GTYP

This blog post discusses the differences between designing with UltraScale+ GTY and Versal GTY/GTYP

N/A

https://forumssupport.xilinx.com/t5/Design-and-Debug-Techniques-Blogs/article/Differences-Designing-with-UltraScale-GTY-and-Versal-GTY-GTYP/ba-p/1271972?language=en_US

N/A

PS-GEM

This blog demonstrates how to bring up the PS-GEM in Versal.

VCK190

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Bringing-Up-a-1G-Ethernet-Interface-on-a-Versal-device/ba-p/1092703

2020.2

PS and PL based Ethernet

This GitHub repo contains design files demonstrating a PS 10/100/1000BASE-T design utilizing the GEM over MIO to the TI PHY onboard on the VCK190

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet

2021.1

PL 1G Ethernet

This project is about building Versal based AXI 1G/2.5G Ethernet Subsystem example design and testing it by targeting on VCK190 ACAP device using SGMII SFP

VCK190

https://github.com/Xilinx-Wiki-Projects/VCK190-Ethernet/tree/master/2020.2/pl_eth_1G

2020.2

MRMAC

This blog covers the key differences between designing with UltraScale+ CMAC and Versal MRMAC.

Any

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Differences-between-Designing-with-UltraScale-CMAC-and-Versal/ba-p/1209580

2020.2

AI Engine tools, graphs, kernels and compiler

Series of blog posts that demonstrates how to get started with AI Engine tools, graphs, kernels and compiler.

VCK190

https://forumssupport.xilinx.com/s/t5/AI-Engine-DSP-IP-and-Tools/Xilinx-Versal-AI-Engine-Series-Articles/td-p/1191630question/0D52E00006xR6iXSAS/ai-engine-blog-series

2020.2