Table of Contents |
---|
Introduction
Table of Contents |
---|
Introduction
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AdvancedMicrocontroller Bus Architecture (AMBA®) AXI and provides the controller interface for asynchronous serial
data transfer. This soft IP core is designed to connect through an AXI4-Lite interface.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
uartns550 | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartns550 | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550 |
Info |
---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartns550 |
The driver source code is organized into different folders. The table below shows the uartns550 driver source organization.
Directory | Description |
---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer https://www.xilinx.com/support/documentation/ip_documentation/ds748_axi_uart16550.pdf
Features
...
Code Block |
---|
Successfully ran Uartns550 hello world Example |
Example Design Architecture
NA
Change Log
2021.2
None
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L64
...