Table of Contents
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The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between MIPI-based image sensors and an image sensor pipe. An internal high speed physical layer design, D-PHY, is provided that allows direct connection to image sources.
IP/Driver Features
| IP Features | 2018.1 | 2018.2 | 2018.3 | 2019.1 | 2019.2 | 2020.1 | 2020.2 | 2021.1 | 2021.2 |
|---|---|---|---|---|---|---|---|---|---|
| IP version | 3.0 | 3.0 | 4.0 | 4.0 | 4.1 | 5.0 | 5.1 | ||
| Support for 1 to 4 D-PHY lanes | NA | ||||||||
| Line rates ranging from 80 to 1500 Mb/s | NA | ||||||||
| Multiple Data Type support (RAW, RGB, YUV) | IP allows RAW6/7/8/10/12/14, all RGB and YUV 422 8bpc Driver allows to set any format except when RAW10 and RAW12. | IP allows RAW6/7/8/10/12/14/16/20, all RGB and YUV 422 8/10 bpc Driver allows to set any format except when RAW10, RAW12 and RAW16 | Added YUV 420 8 bpc support | ||||||
| AXI IIC support for Camera Control Interface (CCI) | NA | Removed | |||||||
| Filtering based on Virtual Channel Identifier | NA | ||||||||
| Support for 1, 2, or 4 pixels per sample at the output | Yes** | ||||||||
| AXI4-Lite interface for register access to configure different subsystem options | Yes | ||||||||
| Dynamic selection of active lanes within the configured lanes during subsystem generation | Yes | ||||||||
| Interrupt generation to indicate subsystem status information | Yes | ||||||||
| Internal D-PHY allows direct connection to image sources | Yes | ||||||||
| Resource optimization (removed register interface) | NA | No | |||||||
*Only RAW8/10/12/16 media bus formats are tested.
**Tested for 1 and 2 pixels per sample
Update for 2021.1
Since 2021.1, the upstream driver is being used. This driver doesn't have any of the v4l2 controls as earlier.
Now pad 0 is sink pad and pad 1 is source pad. It uses the gpio connected to video-aresetn pin to reset.
In case of buffer overflow, the core is disabled.
It enumerates the bus formats. Only the sink pad format can be set. When trying to set source format, driver will return the format set on sink pad.
The driver just reads and prints the short packet data now to debug log when the Short packet FIFO is not empty.
It still keeps a counter of all types of events and prints them on log status.
Now on stream on, the driver not only enables itself but calls the stream on function of the driver for source element (reliance on Xilinx video pipeline is reduced).
On stopping stream, the core is disabled and a hard reset via gpio connected to video-aresetn pin is given to core.
Missing Features / Known Issues / Limitations in Driver
- If Stream line buffer full prints / events come, the design needs to be checked.
- There is no separate DPHY Phy driver.
- When DPHY register interface is enabled, the driver only enables or disables the DPHY. It doesn't support modification of other DPHY parameters.
- The driver is tested with fixed clocks.
- The driver has always been tested with Video Format Bridge enabled.
- Power suspend / resume are not tested.
- Resource optimized IP (no register interface) not supported.
Other features supported in driver are -
- Configure the number of active lanes. (removed in upstream)
- Notification on reception of short packets. (removed in upstream)
- Getting short packet data using new event type. (removed in upstream)
- Notification on short packet FIFO overflow. (removed in upstream)
- Notification on stream line buffer overflow. (removed in upstream, driver stops IP so system is not hung and pipeline can be restarted)
- Get the number of frames received since streaming is enabled.
- Print driver counters keeping track of number of interrupt / error events
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Test Procedure
A video pipeline with MIPI CSI2 Rx connected to Demosaic, Gamma LUT, VPSS CSC, VPSS Scaler and Framebuffer Write IP is created for ZCU102 board.
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#Assume MIPI CSI2 Rx subsystem which is registered as /dev/v4l-subdev1
#To set the number of active lanes as 4 (NA after 2020.2)
yavta -w '0x0098c981 4' /dev/v4l-subdev1
#To see all the controls
yavta -l /dev/v4l-subdev1
#Need to setup the media pipeline and start capture of video stream
media-ctl -v -V '"IMX274":0 [fmt:SRGGB8/1920x1080@1/60 field:none colorspace:srgb]' -d /dev/media1
media-ctl -v -V '"a00f0000.csiss":0 [fmt:SRGGB8_1X8/1920x1080 field:none colorspace:srgb]' -d /dev/media1
media-ctl -v -V '"a0250000.v_demosaic":1 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1
media-ctl -v -V '"a0270000.v_gamma":1 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1
media-ctl -v -V '"a0240000.csc":1 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1
media-ctl -v -V '"a0200000.scaler":0 [fmt:RBG888_1X24/1920x1080 field:none colorspace:srgb]' -d /dev/media1
media-ctl -v -V '"a0200000.scaler":1 [fmt:UYVY/1920x1080 field:none colorspace:srgb]' -d /dev/media1
#Now start streaming
yavta -n 3 -c10 -f UYVY -s 1920x1080 --skip 7 -F /dev/video4
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Known Issues
- AR67896 - MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2016.3 tool and later versions
Change log
2021.2
- No changes
2021.1
- Summary
- Fix warnings for NULL_RETURNS
- Add YUV 420 8 bpc support
- Upstream version being used
- Commits
2020.2
- Summary
- Add support for YUV 420 8 bpc
- Fix Coverity warnings
- Commits
2020.1
- Summary
- I2C has been removed and DPHY is now at 4K offset. So IP and driver version has been set to 5.0
- Set source pad format same as sink pad
- Instead of 1, set default number of active lanes as max number of lanes
- Commits
- v4l: xilinx: xcsi2rxss: Move DPHY offset to 4K instead of 64K
- dt-bindings: media: xilinx: csi2rxss: Add 5.0 compatible string
- v4l: xilinx: xcsi2rxss: Add v4.1 compatible string
- dt-bindings: media: xilinx: csi2rxss: Add 4.1 compatible string
- v4l: xilinx: xcsi2rxss: Set default active lanes to max
- v4l: xilinx: xcsi2rxss: Source pad has same format as sink pad
2019.2
- Summary
- Add support to reset IP using external GPIO and stop streaming in case of stream line buffer full condition.
- Commits
- c3e2148 v4l: xilinx: xcsi2rxss: Use external reset in a SLBF condition
2019.1
- Summary
- Add support for common clock framework
- Add support for RAW16 format
- Commits
2018.3
- Summary
- Add support for up to 16 virtual channel VCX when enabled in IP configuration
- Fix to store format size to ensure link_validate passes.
- Commits
2018.2
- Summary
- No changes
2018.1
- Summary
- Add xlnx,mipi-csi2-rx-subsystem-3.0 compatible string
- Fix compilation issue due to framework change
- Commits
2017.4
- Summary
- No changes
2017.3
- Summary
- Fix to handle failure case while creating a custom control
- Commits
- 9921a92 v4l: xilinx: csi2rxss: Handle failing to create custom control
2017.2
- Summary
- Fix a crash caused by update to events counters
- Commit
- e3a7ef8 xcsi2rxss: Fix crash caused by update to event counter variable
2017.1
- Summary
- Fix to support changing the bayer phase at run time
- Commit
- 56e9ba9 xcsi2rxss: Support bayer phase change at run-time
2016.4
- Summary
- No change
2016.3
- Summary
- The driver is added
- Commits
- 4db32c67 xcsi2rxss: Add support for Xilinx CSI-2 Receiver Subsystem
Related Links
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