The purpose of this page is to describe the Linux V4L2 driver for Xilinx MIPI Camera Serial Interface 2 Receiver subsystem (MIPI CSI2 Rx SS) soft IP. The Linux MIPI CSI2 Rx Subsystem driver (xilinx-csi2rxss.c) is based on the V4L2 framework, and creates a subdev node(/dev/v4l-subdev*) which can be used to configure the MIPI CSI2 Rx Subsystem IP core. The general description of V4L2 framework is documented here, v4l2-framework.txt. This subdev driver has 2 ports. One sink port which is connected to the image sensor's source port and one source port. The media format applied on the sink port is passed on to the source port. The media format applied is validated based on the IP configuration like RAW8, RAW10, etc. The driver also exposes a V4L2 control to set the number of active lanes, if the feature is enabled in the IP configuration. It also exposes V4L2 control to read number of frames transferred and to reset the event counters.
The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between MIPI-based image sensors and an image sensor pipe. An internal high speed physical layer design, D-PHY, is provided that allows direct connection to image sources.
|Support for 1 to 4 D-PHY lanes||NA|
|Line rates ranging from 80 to 1500 Mb/s||NA|
|Multiple Data Type support (RAW, RGB, YUV)|
IP allows RAW6/7/8/10/12/14, all RGB and YUV 422 8bpc
Driver allows to set any format except when RAW10 and RAW12.
IP allows RAW6/7/8/10/12/14/16/20, all RGB and YUV 422 8/10 bpc
Driver allows to set any format except whenRAW10, RAW12 and RAW16
Added YUV 420 8 bpc support
|AXI IIC support for Camera Control Interface (CCI)||NA||Removed|
|Filtering based on Virtual Channel Identifier||NA|
|Support for 1, 2, or 4 pixels per sample at the output||Yes**|
|AXI4-Lite interface for register access to configure different subsystem options||Yes|
|Dynamic selection of active lanes within the configured lanes during subsystem generation||Yes|
|Interrupt generation to indicate subsystem status information||Yes|
|Internal D-PHY allows direct connection to image sources||Yes|
|Resource optimization (removed register interface)||NA||No|
*Only RAW8/10/12/16 media bus formats are tested.
**Tested for 1 and 2 pixels per sample
Missing Features / Known Issues / Limitations in Driver
- If Stream line buffer full prints / events come, the design needs to be checked.
- There is no separate DPHY Phy driver.
- When DPHY register interface is enabled, the driver only enables or disables the DPHY. It doesn't support modification of other DPHY parameters.
- The driver is tested with fixed clocks.
- The driver has always been tested with Video Format Bridge enabled.
- Power suspend / resume are not tested.
- Resource optimized IP (no register interface) not supported.
Other features supported in driver are -
- Configure the number of active lanes.
- Notification on reception of short packets.
- Getting short packet data using new event type.
- Notification on short packet FIFO overflow.
- Notification on stream line buffer overflow.
- Get the number of frames received since streaming is enabled.
- Print driver counters keeping track of number of interrupt / error events
MIPI CSI-2 Rx Subsystem IP Release Notes and Known Issues
The following configs need to be enabled
Device Tree BindingThe dts node should be defined with correct hardware configuration.
A video pipeline with MIPI CSI2 Rx connected to Demosaic, Gamma LUT, VPSS CSC, VPSS Scaler and Framebuffer Write IP is created for ZCU102 board.
An IMX74 sensor FMC card is used to capture image and send CSI stream to MIPI CSI 2 Rx Subsystem.
media-ctl is used to set the color format on the pads.
Using v4l2-ctl to set the number of active lanes
Using yavta to set the number of active lanes
A custom application was implemented to test getting the short packets and other events using poll() on file descriptor returned on open() of the v4l subdev.
This was done as poll() mechanism on sub device wasn't present in any standard application.
Driver has been tested on following boards:
- AR67896 - MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2016.3 tool and later versions
- Add support for YUV 420 8 bpc
- Fix Coverity warnings
- I2C has been removed and DPHY is now at 4K offset. So IP and driver version has been set to 5.0
- Set source pad format same as sink pad
- Instead of 1, set default number of active lanes as max number of lanes
- Add support to reset IP using external GPIO and stop streaming in case of stream line buffer full condition.
- c3e2148 v4l: xilinx: xcsi2rxss: Use external reset in a SLBF condition
- Add support for common clock framework
- Add support for RAW16 format
- 9bd3a62 v4l: xilinx: xcsi2rxss: Add support for RAW16 format
- c3659f0 v4l: xilinx: xcsi2rxss: Add support for clock framework
- Add support for up to 16 virtual channel VCX when enabled in IP configuration
- Fix to store format size to ensure link_validate passes.
- Add xlnx,mipi-csi2-rx-subsystem-3.0 compatible string
- Fix compilation issue due to framework change
- Fix to handle failure case while creating a custom control
- 9921a92 v4l: xilinx: csi2rxss: Handle failing to create custom control
- Fix a crash caused by update to events counters
- e3a7ef8 xcsi2rxss: Fix crash caused by update to event counter variable
- Fix to support changing the bayer phase at run time
- 56e9ba9 xcsi2rxss: Support bayer phase change at run-time
- 4db32c67 xcsi2rxss: Add support for Xilinx CSI-2 Receiver Subsystem