Intc
Introduction
The LogiCORE™ IP AXI Interrupt Controller (INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single interrupt output to the system processor. The registers used for storing interrupt vector addresses, checking, enabling and acknowledging interrupts are accessed through the AXI4-Lite interface.
HW/IP Features
Support up to 32 interrupt inputs
Capable of cascading
Enabling and disabling of individual interrupts.
Capable of generating software interrupts
Features supported in driver
- Single AXI INTC IP supports 32 interrupts, multiple AXI INTC IP's can be cascaded, to support more than 32 interrupt inputs
- Supports chaining with GIC "PL peripheral→ AXI INTC→ GIC→ ARM processor"
- Experimental support to load driver as module
Devicetree
| Code Block | ||
|---|---|---|
| ||
axi_intc_1: interrupt-controller@41200000 {
#interrupt-cells = <2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = <0x41200000 0x10000>;
xlnx,kind-of-intr = <0x1>;
xlnx,num-intr-inputs = <0x3>;
}; |
Mainline status
Existing driver https://github.com/Xilinx/linux-xlnx/blob/master/drivers/irqchip/irq-xilinx-intc.c is in sync with mainline.
...
| Code Block | ||
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NR_IRQS:33 /amba_pl/interrupt-controller@41200000: num_irq=3, edge=0x1 |
References
AXI Interrupt Controller (INTC) v4.1 Product Guide
Cascade Interrupt Controller support in DTG