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AXI CDMA Standalone Driver
Table of Contents
| Table of Contents |
|---|
AXI CDMA Standalone Driver
Introduction
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Table of Contents
| Table of Contents | ||
|---|---|---|
|
Introduction
The AXI CMDA core is a soft Xilinx
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IP
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core for use with the Xilinx Vivado® Design Suite. The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. An optional Scatter Gather (SG) feature can be used to offload control and sequencing tasks from the system CPU. Initialization, status, and control registers are accessed through an AXI4-Lite slave interface.
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How to enable
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For more information, please refer to the AXI CDMA product page which includes links to the official documentation and resource utilization.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
<If there are multiple drivers supporting this IP, we should make that statement here and add to the table>
| Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| axicdma | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axicdma_<version> | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axicdma |
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| Info |
|---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axicdma |
The driver source code is organized into different folders.
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The table below shows the axicdma driver source organization.
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| Directory |
|---|
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| Description |
|---|
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| doc |
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Provides the API and data structure details |
| data |
| Driver .tcl and |
| .mdd file |
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| examples | Example applications that show how to use the driver |
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| features | |
| src | Driver source files |
Features Supported
Controller Features
- AXI4 interface for data transfer
- Independent AXI4-Lite slave interface for register access
- Independent AXI4 Master interface for
- Optional Scatter/Gather(SG) function
- Optional Data Realignment Engine
- Register Direct Mode
- Optional Scatter-Gather DMA support
- Optional Store and Forward support
- Parameterized Read and Write Address Pipeline depths
- Fixed-address and incrementing-address burst support
- Support for up to 64-bit addressing
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Driver Implementation
For a full list of features supported by this IP, please refer to the AXI CDMA product page.
Features
The AXI CDMA Standalone driver supports the ...
- Supports Simple DMA mode
- Supports Scatter/Gather Direct Memory Access (DMA)
- Supports 64-bit Addressing
- Supports Optional Data Re-Alignment Feature
- Supports Register Direct mode
Test cases
- Refer below pah for testing different examples for each feature of the IP.
Known Issues and Limitations
- All IP features are supported
Example Design Architecture
For simple/SG mode the examples assumes AXI CDMA Data AXI4 Read/Write MasterIP M_AXI/M_AXI_SG interface are connected to DDR.
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axicdma/examples
| Test Name | Example Source | Description |
|---|---|---|
| Scatter Gather DMA with Interrupts | xaxicdma_example_sg_intr.c |
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| This example demonstrates how to transfer packets in interrupt mode when the core is configured in SG Mode. | |
| Scatter Gather DMA with Polling | xaxicdma_example_sg_poll.c |
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| This example demonstrates how to transfer packets in the polled mode when the core is configured in SG Mode. | |
| Simple DMA with Interrupt | xaxicdma_example_simple_intr.c |
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| This example demonstrates how to transfer packets in interrupt mode when the core is configured in simple DMA Mode. | |
| Simple DMA with Polling | xaxicdma_example_simple_poll.c |
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| This example demonstrates how to transfer packets in the polled mode when the core is configured in simple DMA Mode. | |
| Hybrid(SG+ simple) with Interrupts | xaxicdma_example_hybrid_intr.c |
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| This example demonstrates how to transfer packets in interrupt mode when the core is configured in hybrid(SG + simple) transfer Mode. | |
| Hybrid(SG+ simple) with Polling | xaxicdma_example_hybrid_poll.c |
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This example demonstrates how to transfer packets in the polled mode when the core is configured in hybrid(SG + simple) transfer Mode. |
Example Application Usage
Scatter Gather with Interrupts
This example demonstrates how to transfer packets in interrupt mode when the core is configured in SG Mode.
Known issues and Limitations
- All IP features are supported
Change Log
2020.2
- Consolidate debug header files.
- Fix axicdma hybrid interrupt/poll example failures.
- Support parallel make execution.
257c0d9e3742 BSP: Consolidate and add the drivers xdebug.h data to common xdebug.h
4dc85994d6fb Makefile: Remove realpath command
bc81851ae0d5 axicdma: Fix axicdma hybrid interrupt example failure
7b40e2e94d9b axicdma: Fix xreg_cortexa9.h compilation error on R5 processor
73ffe7217f1c axicdma: Update Makefile to support parallel make execution
fab4922c382d axicdma: Fix xaxicdma_example_hybrid_poll example failure
d6191ca046d2 axicdma: To fix the compilation error
2020.1
- Fix race condition in driver tcl.
- Cleanup old axicdma driver version.
- Fix gcc warning in peripheral test and examples.
- Support 26bit dma transfer length.
097fb0b drivers: axicdma: Fix race condition in the test app tcl
f70c6fc axicdma: Clean up old versions for axicdma driver
985f002 axicdma: Fix gcc warning in peripheral test and examples
952386c axicdma: Support 26bit dma transfer length
2019.2
- Fix cache maintenance operation for data buffers in examples.
- Enable debug prints in examples.
Commit Id's
67fe31f axicdma: examples: Fix cache maintenance operation for data buffers
320aa07 axicdma: examples: Add errors prints for failing scenarios
2019.1
- None
2018.3
- Fix typos in peripheral app tcl.
- Reset error and done states before starting DMA.
- Fix compilation error in examples DEBUG mode.
- Fix gcc and cppcheck warnings.
Commit Id's
20df53d Fix typos in peripheral app generation tcl
394e44f examples: Reset error and done states before starting DMA
5e68393 examples: Fix compilation error in DEBUG mode
da70e17 Fix gcc warning in peripheral test application
f80f1ad Fix cppcheck warning
cd5bc3d Include missing initializers for 'XAxiCdma_Config' fields
2018.2
- None
2018.1
- Extend AXI CDMA examples to support data buffers above 4GB
Commit Id's
9fab83a axicdma: Extend AXI CDMA examples to support data buffers above 4GB
2017.4
- None
2017.3
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Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
Successfully ran XAxiCdma_SgIntr Example
--- Exiting main() ------ Entering main() --- |
Scatter Gather with Polling
This example demonstrates how to transfer packets in the polled mode when the core is configured in SG Mode.
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
Successfully ran XAxiCdma_SgPoll Example
--- Exiting main() --- |
Simple DMA with Interrupts
This example demonstrates how to transfer packets in interrupt mode when the core is configured in simple DMA Mode.
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
Successfully ran XAxiCdma_SimpleIntr Example
--- Exiting main() ------ Entering main() --- |
Simple DMA with Polling
This example demonstrates how to transfer packets in the polled mode when the core is configured in simple DMA Mode.
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
Successfully ran AxiCdma_SimplePoll Example
--- Exiting main() ------ Entering main() --- |
Hybrid(SG+ simple) with Interrupts
This example demonstrates how to transfer packets in interrupt mode when the core is configured in hybrid(SG + simple) transfer Mode.
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
First simple transfer successful
Scatter gather transfer successful
Second simple transfer successful
Successfully ran Axicdma Hybrid interrupt Example
--- Exiting main() |
Hybrid(SG+ simple) with Polling
This example demonstrates how to transfer packets in the polled mode when the core is configured in hybrid(SG + simple) transfer Mode.
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
First simple transfer successful
Scatter gather transfer successful
Second simple transfer successful
Successfully ran Axicdma Hybrid polled Example
--- Exiting main() |
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L396
Related Links