Introduction
This page gives an overview of UART 16550 driver which is available as part of the Xilinx Vivado and SDK distribution.
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the Advanced
Microcontroller Bus Architecture (AMBA®) AXI and provides the controller interface for asynchronous serial
data transfer. This soft IP core is designed to connect through an AXI4-Lite interface.
Source path for the driver:
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| uartns550 | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartns550 | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550 |
| Info |
|---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartns550 |
The driver source code is organized into different folders.
Below diagramThe table below shows the
iicpsuartns550 driver source organization
uart 16550
|
-- Doc -
.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
|
- Examples - Reference application to
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver |
|
- Source - Driver source files
Controller Features Supported:
features | |
| src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer https://www.xilinx.com/support/documentation/ip_documentation/ds748_axi_uart16550.pdf
Features
- AXI4-Lite interface for register access and data transfers
- Hardware and software register compatible with all
- standard 16450 and 16550 UARTs
- Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity
- Implements all standard serial interface protocols
- 5, 6, 7 or 8 bits per character
- Odd, Even or no parity detection and generation
- 1, 1.5 or 2 stop bit detection and generation
- Internal baud rate generator and separate receiver clock input
- Modem control functions
- Prioritized transmit, receive, line status and modem control interrupts
- False start bit detection and recover
- Line break detection and generation
- Internal loopback diagnostic functionality
- 16 character transmit and receive FIFOs
Known Issues and Limitations
None
Driver Supported Features
The UART 16550 Standalone driver support the below things.All Controller Features supported.
Known issues and Limitations
- None.
Test cases
Refer below pah for testing different examples for each feature of the IP.https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550/examples
ChangeLog
2017.1Summary:
- uartns550: Added xil_printf statement in examples
- uartns550: Updated makefile
- uartns550: Added readme.txt file to generate doxygen for examples
- 35c078f uartns550: Added xil_printf statement in examples
- 1973ac5 uartns550: Updated makefile
- f47abd4 uartns550: Added readme.txt file to generate doxygen for examples
Summary:
- uartns550: Added Suffix U for macros in xparameters.h
- cb54089 uartns550: Added Suffix U for macros in xparameters.h
- None
- None
2018.1
- None
2018.2
- None
2018.3
- None
2019.1
- None
2019.2
- None
2020.1
- Summary
- uartns550: Update the macro names for the DLL and DLM registers
- uartns550: Clean up the options in xuartns550_intr_example
- Commits
2020.2
None| Uartns550 interrupt example | xuartns550_intr_example.c | This example sends and receives data using interrupts |
| Uartns550 polled example | xuartns550_polled_example.c | This example sends and receives data using polling |
| Uartns550 hello world example | xuartns550_hello_world_example.c | This example transmits "Hello world" string |
Example Application Usage
Uartns550 interrupt example
This example sends and receives data using interrupts
Expected Output
| Code Block |
|---|
Successfully ran Uartns550 interrupt Example |
Uartns550 polled example
This example sends and receives data using polling| Code Block |
|---|
Successfully ran Uartns550 polled Example |
Uartns550 hello world example
This example transmits "Hello world" string| Code Block |
|---|
Successfully ran Uartns550 hello world Example |
Example Design Architecture
NA
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L64
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L708
2020.1
2019.2
None
2019.1
None