Table of Contents |
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Introduction
This page gives an overview of nandps driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
The static memory controller (SMC) can be used either as a NAND flash controller or a parallel port memory controller supporting the following memory types:
• NAND flash
• Asynchronous SRAM
• NOR flash
The operational registers of the SMC are configured through an APB interface. The SMC handles all commands, addresses, data, and the memory device protocols. It allows the users to access the controller by reading or writing into the operational registers. The SMC is based on Arm's PL353 static memory controller.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
nandps | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/nandps | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandps |
Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/ |
The driver source code is organized into different folders.
The table below shows the
nandps driver source organization.
Directory | Description |
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doc |
Provides the API and data structure details |
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- Examples - Reference application to
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver |
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- Source - Controller Features:
features | |
src | Driver source files |
Features Supported
Driver Implementation
For a full list of features supported by this IP, please refer Chapter 11: Static Memory Controller in Zynq TRM.
Features
- ONFI 1.0 compatible
- upto 1GB device
- 8/16-bit IO width with a single chip select
- 16-word read/write FIFOs
- 8-word command FIFO
- Programmable IO Cycle timing
- 1-bit ECC hardware with sw assist
- Asynchronous memory operating mode
- Supports only the mandatory ONFI 1.0 commands. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features
- supports page cache read operations
- Support BBT management
- Support for ondie ecc devices
Bad Block management
As part of the bbt management, driver reserves the last 4 blocks of the flash device for storing the bbt information. bbt management is similar to the Linux except the offset of storing the BBT signature land version location and also the locations reserved for storing the ecc information.Nandps exampleKnown issues and Limitations
- Driver supports polled mode only
- No support for interleaved and optional 1.0 commands
ChangeLog
2016.3
- None
2016.4
- None
2017.1
- None
2017.2
- None
2017.3
- None
2017.4
- None
2018.1
- None
2018.2
- None
2018.3
- Summary
- Fix incorrect BBT write
- Commit
- Summary
2019.1
- None
2019.2
- None
2020.1
- None
2020.2
- Summary
- Update Makefile for parallel make execution
- Commits
- Summary
Test cases
Supported Flash vendors
- Micron
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/
blob/mastertree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/nandps/examples
/Test Name | Example Source | Description |
---|---|---|
NANDPS Example | xnandps_example.c |
In this process erase, program, read, read ID, Read Parameter Page, Reset, read status, get/set features and bbt management are covered
Output:
his examples does basic read and write test from the NAND flash device | ||
NANDPS Cache Example | xnandps_cache_example.c | This example tests Page cache read & write command on NAND Flash Device. |
NANDPS Skip Block Example | xnandps_skip_example.c | This example tests the skip block method of erase/read/write operation on NAND Flash Device. |
Example Application Usage
NANDPS Example
This examples does basic read and write test from the NAND flash device.
Nand Flash Read Write Example Test Successfully ran Nand Flash Read Write Example |
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Nandps skip example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/nandps/examples/xnandps_skip_example.cSame as nandps example. In addition to that it will verify the given block is bad or not. if it is bad block it skips that block and proceed with other good block.
Output:
theme | Midnight |
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Test |
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NANDPS Cache Example
This example tests Page cache read & write command on NAND Flash Device.
Nand Flash Read Write Example Test Successfully ran Nand Flash |
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Read |
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Write Example Test |
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Nandps cache example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/nandps/examples/xnandps_cache_example.cSame as nandps example. In addition to that it will use the page cache read operations.
Output:
theme | Midnight |
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NANDPS Skip Block Example
This example tests the skip block method of erase/read/write operation on NAND Flash Device
Nand Flash Skip Block Method Example Test Successfully ran Nand Flash |
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Skip Block |
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Method Example Test |
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Example Design Architecture
NA
Performance
Write( |
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mbps) | Read( |
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mbps) | |
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7.1 | 13.8 |
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L451
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L633
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L503
2019.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L1954
2019.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L1715